Electronics Design AUMAX31865 reading fault bit on every conversion — VBIAS enabled but still faulting
Asked by stale_biscuit_03 ·
Spent most of yesterday trying to get a MAX31865 talking to my STM32F4 and I'm stuck on the same problem no matter what I try: the fault bit (bit 0 of register 0x02) is set on every single conversion. Doesn't matter how many times I retry.
My setup: 430Ω reference resistor, 2-wire PT100 probe, 3.3V supply. Writing 0xC0 to the config register (address 0x80) to enable VBIAS and auto-conversion in 2/4-wire mode.
I added a 100ms delay after writing the config before attempting any reads — so the VBIAS should have plenty of time to settle. Still faulting. The 16-bit RTD register comes back as 0x7FFF every time (or 0x0001 when I shift out the fault bit, which is basically zero).
I know the fault bit indicates something's wrong in the measurement chain, but I'm not sure where to start diagnosing it. Do I need to write something special to clear it? I tried toggling VBIAS off and on but that didn't help either.
3 Replies
The fault bit in the RTD register tells you that a fault exists — it doesn't tell you what the fault is. That information lives in the fault status register at address 0x07. Read that register first and check which bits are set. Without it you're guessing.
The bits to look at:
-
D3 (RTDIN- below 0.85 × VBIAS): The RTD or its wiring is open. On a 2-wire setup, this usually means RTDIN- isn't connected, or FORCE2 (which should be tied directly to RTDIN-) is floating. The RTD code
0x7FFFyou're seeing — maximum raw value — is consistent with RTDIN- pulled high through an undriven path, which points straight at this fault. -
D4 (REFIN- below 0.85 × VBIAS) or D5 (REFIN- above 0.85 × VBIAS): The reference resistor path has a problem. Check that your 430Ω resistor is connected from FORCE1 to REFIN+, and that REFIN- connects to RTDIN+ (the node between the reference resistor and the top of the RTD). If REFIN- is connected to GND instead of RTDIN+, you'll get a REFIN fault on every conversion regardless of VBIAS state.
-
D7 (RTD high threshold): Less common on bring-up, but set if the measured resistance is above the internal high threshold register default — also consistent with RTDIN- being high-impedance.
The 0xC0 delay you added is fine for VBIAS settling (typically the datasheet specifies waiting around 10 ms before the first conversion, so 100 ms is more than enough). VBIAS timing is probably not your issue — a floating RTDIN- or a mis-wired REFIN- would cause exactly what you're seeing.
One more thing: fault bits on the MAX31865 are latched. They won't clear on their own after you fix the wiring. Write bit 1 of the config register (set D1 = 1, e.g. write 0xC2 to address 0x80) to clear them, then immediately read back the fault register again to confirm the fault is gone after you've resolved the wiring.
The MAX31865 guide has the full fault register bit map and wiring diagram if you need a reference while debugging.
Before diagnosing the fault register contents, do a sanity check: read back the config register at address 0x00 and verify it actually contains 0xC0.
MAX31865 uses SPI with CPHA = 1. That's Mode 1 (CPOL=0, CPHA=1) or Mode 3 (CPOL=1, CPHA=1). If your STM32 SPI peripheral is initialised in Mode 0 (CPHA=0, CPOL=0), every write transaction is being silently ignored by the MAX31865 and every read returns undefined garbage. The chip defaults to 0x00 in the config register, so if your read-back shows 0x00, that's the diagnostic — you're not communicating with it at all.
Also check your CS timing: CS needs to go low before the first clock edge and stay low for the entire transaction. Toggling CS in the middle of a byte or releasing it early causes the same symptoms.
When thermocouple_ted mentions checking the REFIN- connection, here's what to specifically verify on the schematic: the 430Ω reference resistor must sit between FORCE1 and REFIN+, and REFIN- must connect to the same node as RTDIN+ — not to GND, not to VCC.
A common mistake is wiring the reference resistor from VCC to REFIN+ instead of from FORCE1. The IC's bias circuit is on FORCE1, not VCC — if RREF is tied to VCC instead, the REFIN+ voltage is set by the supply, not the measurement current, and the ratiometric measurement breaks entirely. Depending on the exact voltages, this triggers either the REFIN below or above threshold fault bits.
Similarly, REFIN- connected to GND (instead of RTDIN+) puts REFIN- at 0V regardless of what the measurement chain is doing, which reliably triggers fault bit D4.
One more thing while you're auditing the connections: confirm you have 430Ω specifically, not 470Ω (the nearest E24-series value). The wrong resistor value doesn't cause a fault directly, but it shifts every temperature reading proportionally — so after you fix the fault, if your readings are consistently off by roughly 9%, that's the resistor. The PT100 fundamentals article has context on the ratiometric measurement chain and why the reference resistor value matters as much as its placement.
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