Logic Analyser vs Oscilloscope: Which Should You Use?

Detailed Explanation

Both instruments observe signals on digital PCB traces. The difference is in what they measure and how they represent it.

An oscilloscope captures the actual voltage waveform — a continuous analog measurement showing every volt and every nanosecond of detail. It reveals signal integrity: whether a signal overshoots, whether a rise time is clean, whether a power rail stays within tolerance during a load transient. Its weakness is channel count — most bench oscilloscopes have 2–4 channels, and its display is optimised for a few signals at once.

A logic analyser treats every channel as a binary threshold: above the configured logic-HIGH threshold, the channel is HIGH; below it, LOW. It does not measure voltage. What it does instead: it samples many channels simultaneously (8, 16, or more) and can capture millions of samples per channel, and its software decodes those binary streams into human-readable protocol frames — "I2C: START, address 0x48, W, ACK, data byte 0xA3, STOP." Its weakness is that it cannot tell you anything about analog behaviour — a logic analyser on an I2C bus with 100 kΩ pull-up resistors may show the bus toggling apparently correctly, while an oscilloscope on the same bus would reveal the dangerously slow edges that will cause reliability problems.

When to Use a Logic Analyser

Protocol transaction debugging: You've implemented I2C firmware and the device is not responding. Is the address correct? Is the firmware sending the right bytes? Is the device ACKing? Hook a logic analyser to SDA and SCL and decode the transaction — you'll see the exact address, data, ACK/NACK, and timing, compared against the device datasheet. A two-channel oscilloscope can show you the same waveform, but you'd need to decode the bit sequence manually from the trace — tedious for anything beyond the first few bytes.

Multi-signal timing relationships: A SPI transaction involves CS, SCLK, MOSI, and MISO — four signals that must be observed simultaneously and correlated. An oscilloscope with 4 channels can show them all, but a logic analyser decodes the bytes automatically and shows you "SPI: byte 0x45 transmitted, byte 0x0A received" rather than a waveform you must manually decode.

Long captures: A logic analyser captures seconds or minutes of protocol activity across many channels. An oscilloscope typically captures microseconds to milliseconds per trigger — finding a rare error buried in 10 seconds of I2C traffic is more practical on a logic analyser that captures the full session.

UART at human rates: Debugging a UART at 115200 baud: does the MCU transmit the correct character sequence? Trivial on a logic analyser; tedious on an oscilloscope.

Protocol-specific timing violations: Most logic analyser decoders flag protocol violations — I2C clock-stretch timeouts, UART framing errors, SPI CS timing violations — automatically in the decoded output. SPI clock mode mismatches (CPOL/CPHA) can also be identified by iterating the decoder's phase settings until bytes decode correctly, without touching the firmware — see diagnosing SPI CPOL/CPHA faults via logic analyser for a step-by-step example.

When to Use an Oscilloscope

Signal integrity: A 3.3 V SPI clock with a 10 ns rise time and 500 mV of overshoot is transmitting data correctly at low speeds, but that overshoot may cause intermittent failures at higher speeds or in noisier conditions. A logic analyser shows the data as clean; the oscilloscope shows the problem.

Voltage level verification: Is the 3.3 V rail really 3.3 V? Is an I2C pull-up achieving full logic-HIGH level? Is a GPIO output reaching the full rail, or is it drooping due to weak drive strength and excessive capacitive load? Only the oscilloscope answers these.

Power supply analysis: Measuring ripple, load transient response, turn-on sequencing, and noise coupling from switching regulators — these are all analog quantities requiring an oscilloscope. See oscilloscope basics for measurement technique.

Timing at sub-nanosecond resolution: The oscilloscope's analog bandwidth (100 MHz, 500 MHz, 1 GHz) determines its ability to show edge detail. A logic analyser's binary sampling misses the analog transition detail — it records "went HIGH at time T" but not how the signal got there.

Single-shot events: Power glitches, ESD events, and one-time boot sequences are captured with the oscilloscope in single-trigger mode. A logic analyser can also capture one-shot events, but the binary threshold means it misses any analog behaviour during the event.

Differential signals and balanced pairs: LVDS, RS-485, CAN, and Ethernet PHY signals often require a differential probe and an oscilloscope. Logic analysers typically work with single-ended inputs referenced to ground.

Using Both Together

The most productive debug setup uses a logic analyser and oscilloscope simultaneously:

• Logic analyser on the protocol signals (SDA, SCL, MISO, MOSI, SCLK, CS): shows transactions and flags protocol violations.
• Oscilloscope on the power supply and one or two key signals: shows voltage level, ripple, and signal integrity at the same time.

When a transaction fails (error on the logic analyser), checking the oscilloscope simultaneously shows whether the power supply drooped or whether there was noise at the relevant timestamp. Correlating both views finds problems in minutes that either tool alone would take much longer to diagnose.

Tool Recommendations for Embedded Debugging

A Saleae Logic 8 plus a 2-channel oscilloscope is the most common and cost-effective combination for serious embedded debugging. The Saleae Logic 2 software is particularly well-regarded for its clean UI and comprehensive protocol decode library.

A mixed-signal oscilloscope (MSO) combines digital logic channels with analog oscilloscope channels in one instrument — useful for bench space and trigger cross-correlation. Purpose-built logic analysers with dedicated software are generally more capable for protocol analysis at the same price point.

Design Considerations

• Accessible debug points: Place 1.0 mm test points or 0.1" header pads on SDA, SCL, MISO, MOSI, SCLK, UART TX/RX, and any CAN bus lines. Logic analyser clips attach more reliably to test points than to 0.5 mm pitch IC pins, and reduce the risk of bridging adjacent pins during clip attachment.
• Ground points: Logic analysers need a ground reference on every group of channels. Place a ground test point near the protocol signals being captured — ideally within 50 mm of the signal test points to keep the ground lead short.

Common Mistakes

• Replacing the oscilloscope with a logic analyser for signal integrity work — the logic analyser only shows binary states and cannot diagnose overshoot, noise, or voltage drooping.
• Setting the logic analyser threshold voltage too high or too low for the target logic family — a threshold set at 1.65 V (3.3 V logic midpoint) on a 1.8 V logic device will decode incorrectly because the 1.8 V HIGH is 900 mV below the threshold.
• Capturing a short window and concluding no error occurred — protocol errors can be rare and intermittent. Capture at least several seconds (or until an error is observed) rather than a 1 ms snapshot.
• Forgetting to connect the logic analyser ground lead — floating ground causes all channels to toggle randomly, producing garbage decoded output.