Electronics Design AUERC errors I can't clear after first real schematic — 'PWR_PIN undriven' and 'pin not connected' in KiCad
Asked by stale_biscuit_03 ·
First time drawing a schematic in KiCad that I actually intend to route a real board from, not just for reference. Components placed, wires drawn, ran ERC to check before moving forward and got hit with a wall of errors I don't understand well enough to fix confidently:
- Multiple "Pin not connected" on pins that look connected to me — wire is touching the pin as far as I can see
- "PWR_PIN undriven" on my VCC and GND nets — I have VCC and GND power symbols on the nets, so I don't understand what's "undriven" about them
Especially the second one. The nets have power symbols, the schematic visually looks correct. What is ERC actually checking that I'm missing?
2 Replies
Two separate issues, each with a specific fix — worth understanding what ERC is actually checking in each case before rushing straight to the fix.
"Pin not connected"
This fires when a pin genuinely has no net connection in the netlist, even if it visually looks wired up. Most common cause: a wire that ends fractionally short of the pin — overlapping it on screen but not actually snapped to it. KiCad's ERC doesn't infer connections from proximity; the wire has to terminate exactly on the pin endpoint.
Fix: click on each flagged pin in the ERC output, zoom to 1:1, and check whether the wire terminates precisely on the pin or just near it. If the pin is legitimately unused — an NC pin on an IC, an unused input — place a no-connect flag on it (X marker; press Q in the schematic editor) to tell ERC it's intentional.
"PWR_PIN undriven"
This one is KiCad-specific and catches nearly everyone the first time. KiCad's ERC can't determine from a plain VCC or GND power symbol alone whether that net is actually being driven by a source — it treats power symbols as passive connections unless something on the net has a power-output pin type. To tell ERC the net is externally driven, you add a PWR_FLAG component from KiCad's power library. It's a schematic-only component — no physical part, no BOM entry — that exists purely to set the net's ERC status. Place one connected to each power net that's flagging the error (VCC, GND, 3V3, etc.).
Once both are resolved, re-run ERC. Anything remaining is more likely to be a real connectivity problem rather than a KiCad convention artefact. For context on what ERC is checking and how it differs from the layout-stage design rule check (DRC), see what schematic capture actually does — that distinction is worth having clear before you hit the DRC errors that come later.
One practical note on PWR_FLAG placement: put it directly next to the VCC (or GND, or 3V3) power symbol, not tucked somewhere else on the sheet. Electrically it doesn't matter where on the net it sits, but schematically it reads clearly as "the rail enters here" — which matters when you or someone else is debugging the schematic six months later.
Also worth knowing: on a flat single-sheet schematic, one PWR_FLAG per net is enough. If you ever go to a hierarchical multi-sheet design, you'll need a PWR_FLAG on each sheet that uses the net, not just the top level. Not relevant now, but it will bite you the first time you try hierarchical sheets without knowing about it.