How Do You Select a Crystal Oscillator for an Embedded System?

Detailed Explanation

A crystal oscillator is the source of a precise clock frequency for a microcontroller, SoC, or RF module. Most embedded processors have an internal RC oscillator (fast start-up, convenient, but ±1–3% frequency accuracy), and an external crystal oscillator input (slower start-up, requires PCB components, but ±20–50 ppm accuracy or better). Understanding when each is appropriate and how to correctly specify the passive crystal is a foundational embedded hardware skill.

When an External Crystal Is Required

Internal RC oscillator is sufficient for:

• Applications where communication speed accuracy doesn't matter (most GPIO, control loops, display driving)
• Devices where the communication peripheral uses its own clock recovery (I2C in most modes, SPI in slave mode)
• Ultra-low-power designs that spend most of their time in deep sleep

External crystal is required for:

• USB (Full Speed at 12 Mbps requires ±2500 ppm or better — the internal RC is not specified for USB FS in most MCUs)
• Bluetooth / BLE (±40–75 ppm for BLE — near the limit of even a good passive crystal without TCXO)
• UART at high baud rates over long periods (at 921600 baud, ±1% clock error causes framing errors)
• Any application where the MCU's internal oscillator accuracy is insufficient for the peripheral's timing requirements — the MCU datasheet specifies this per peripheral
• RTC (Real-Time Clock) accurate to within seconds per day — requires 32.768 kHz watch crystal on the LSE pins

Crystal Specifications

Nominal frequency: The resonant frequency at which the crystal is designed to operate. For STM32 HSE, typical ranges are 4–26 MHz — see how the STM32 clock tree uses the HSE input for PLL configuration examples and why HSE accuracy matters for USB and high-speed UART. For LSE/RTC, the standard is 32.768 kHz (2^15 Hz — used because it divides to exactly 1 Hz using a 15-bit counter).

Load capacitance (C_L): The most important parameter to get right. A crystal is specified at a particular load capacitance — the capacitance the oscillator circuit presents at the crystal terminals. Common values are 6 pF, 8 pF, 12 pF, and 18 pF. The load capacitance sets the crystal's oscillation frequency: operating at the wrong C_L shifts the frequency away from the nominal value by tens of ppm.

The load capacitance seen by the crystal is:

C_L = (C1 × C2) / (C1 + C2) + C_stray

Where C1 and C2 are the external load capacitors placed on each crystal pin (typically equal values), and C_stray is the board-level parasitic capacitance on the oscillator traces (typically 1–3 pF per pin, depending on trace length and nearby copper).

If your MCU datasheet specifies 8 pF crystal load capacitance, and your stray capacitance is 2 pF per pin (total 2 pF in the series formula), then:

8 pF = (C1 × C2) / (C1 + C2) + 2 pF
→ C_series = 6 pF
→ C1 = C2 = 12 pF (for equal load caps)

Always calculate rather than using datasheet example values directly — the stray capacitance varies by PCB layout.

ESR (Equivalent Series Resistance): The crystal's internal loss resistance. A higher ESR requires more oscillator gain to sustain oscillation. The MCU's datasheet specifies a maximum ESR the oscillator circuit can drive. The crystal's maximum ESR must be lower than this limit — with some margin.

Typical values:

• 8 MHz AT-cut crystal: ESR 30–100 Ω typical (verify for specific package)
• 32.768 kHz watch crystal: ESR 30–80 kΩ (much higher — requires MCU oscillator circuits designed for this)

Do not use an 8 MHz crystal with an MCU's LSE (32.768 kHz) oscillator, or vice versa — the ESR and drive level are completely incompatible.

Frequency tolerance: How far the oscillation frequency can be from nominal at 25°C, in ppm. ±20 ppm is standard for general-purpose crystals. For comparison: ±20 ppm on 8 MHz is ±160 Hz, or 1.7 µs/day in a RTC.

Frequency stability over temperature: How much the frequency shifts over the operating temperature range, in ppm. AT-cut crystals used in the 1–30 MHz range have a cubic temperature response — at 25°C (the calibration temperature) stability is near zero, and the response is approximately ±30 ppm over -40°C to +85°C. This is separate from the initial accuracy at 25°C.

Drive level: Maximum power the crystal can handle before frequency shifts or damage occurs. Relevant for crystals driven by high-gain oscillator circuits — most MCU oscillators are within the 10–100 µW drive level range that standard crystals tolerate, but verify if you're using a discrete oscillator circuit.

Crystal vs TCXO vs VCTCXO

For BLE, a TCXO or a passive crystal with ±10 ppm or better initial accuracy is required. The Bluetooth specification allows ±40 ppm total frequency error; with a ±20 ppm initial tolerance crystal and ±30 ppm temperature drift, the worst-case total is ±50 ppm — over the limit. In practice many designs use ±20 ppm crystals and work fine, but to be safe, specify ±10 ppm or better initial tolerance for Bluetooth or use a TCXO.

For USB FS (12 Mbps), the clock must be within ±500 ppm of nominal. A ±20 ppm crystal with good temperature stability easily meets this; the MCU's internal RC oscillator typically doesn't.

PCB Layout Rules

• Keep crystal traces short — long traces add stray capacitance, increase coupling to interference, and reduce oscillator startup margin. Target < 5 mm trace length on each OSC pin.
• Do not route other signals (especially digital clock lines) under or adjacent to the crystal traces — radiated coupling from a fast GPIO into the oscillator traces causes frequency modulation or startup instability.
• Place a ground pour around the crystal and oscillator traces (but leave the crystal itself over a void in the ground plane, not over copper — the copper under the crystal adds capacitance through the package stray coupling).
• Place load capacitors directly adjacent to the crystal, ground returns as short as possible.

During PCB bring-up, verify the crystal is oscillating: probe the MCU's OSC_IN or equivalent pin with an oscilloscope. If oscillation is absent, check the supply to the oscillator cell (some MCUs have a separate oscillator enable), verify the crystal is correctly soldered, and measure the load capacitor values with an LCR meter to rule out wrong placement.

Design Considerations

• 32.768 kHz watch crystals are fragile: Unlike MHz crystals that are packaged in ceramic SMD packages and are very robust, 32.768 kHz tuning-fork crystals (cylindrical TH or SMD packages) have a large-area resonating element and high ESR. They are more susceptible to mechanical damage during assembly (vibration, ultrasonic cleaning) and electrical damage from over-drive. Many MCU datasheets specify a maximum oscillator drive current for the LSE circuit — exceed it and the crystal's ESR increases permanently.
• Verify oscillator start-up margin: Calculate or simulate the oscillator's negative resistance (most MCU reference manuals give the oscillator's transconductance at the operating condition). The negative resistance must be at least 5× the total series loss (crystal ESR + stray resistance). ST provides an oscillator design guide for STM32 family MCUs that covers this calculation.

Common Mistakes

• Using the same load capacitor values from a reference design that uses a different PCB with different stray capacitance — leading to systematic frequency offset that shifts the clock outside tolerance.
• Selecting a crystal with ESR near the MCU's maximum specified drive — the crystal starts up at room temperature but fails to start in cold conditions where ESR increases.
• Routing a ground pour directly under the crystal package — the ground copper adds parasitic capacitance to the crystal case and shifts the effective load capacitance.
• Assuming the 32.768 kHz RTC crystal accuracy is adequate for time-keeping without specifying frequency tolerance and then finding the RTC drifts by minutes per day.