What Is an ADC (Analog-to-Digital Converter) and How Does It Work?

Detailed Explanation

The ADC is the bridge between the analog physical world and the digital processor. Every temperature reading, battery voltage measurement, audio sample, and sensor signal that an embedded system processes passes through an ADC. Understanding how an ADC works — its resolution, sample rate, architecture, and limitations — is fundamental to designing reliable measurement systems.

Resolution and the Least Significant Bit (LSB)

An n-bit ADC quantises an analog input voltage that spans from 0V (or a negative reference) to Vref into 2ⁿ discrete digital codes. The smallest voltage change the ADC can distinguish is one LSB (least significant bit):

LSB = Vref / 2ⁿ

Examples:

• 8-bit ADC, Vref = 3.3V: LSB = 3.3 / 256 = 12.9 mV
• 10-bit ADC, Vref = 3.3V: LSB = 3.3 / 1024 = 3.2 mV
• 12-bit ADC, Vref = 3.3V: LSB = 3.3 / 4096 = 0.806 mV
• 16-bit ADC, Vref = 3.3V: LSB = 3.3 / 65536 = 0.050 mV (50 µV)

Higher resolution does not automatically mean better measurements — the actual measurement accuracy is limited by noise, reference accuracy, and signal conditioning. A 12-bit ADC reading a noisy input may have only 10 effective bits (ENOB — effective number of bits). The ENOB is determined by the signal-to-noise-and-distortion ratio (SINAD) of the actual measurement.

Sampling Rate and Nyquist's Theorem

An ADC samples the input voltage at discrete intervals. The sample rate (in samples per second, sps or Hz) determines how fast a changing signal can be captured.

The Nyquist theorem states that the sample rate must be at least twice the highest frequency component in the input signal to avoid aliasing:

f_sample ≥ 2 × f_max

Aliasing occurs when the sample rate is lower than required: frequencies above f_sample/2 (the Nyquist frequency) are "folded back" and appear as lower-frequency artifacts in the output. For a 10 kHz sine wave sampled at 8 kHz, the alias appears at 8000 − 10000 = −2000 Hz → a 2 kHz tone in the output.

To prevent aliasing, an anti-aliasing filter (a low-pass filter with a cutoff below f_sample/2) is placed at the ADC input before sampling. In practice, filter the input to the highest frequency of interest plus some margin, then sample at 2–5× the cutoff frequency.

Example: For ECG monitoring with signal content up to 150 Hz:

• Anti-aliasing filter cutoff: 150 Hz
• Minimum sample rate: 300 sps
• Practical sample rate: 500–1000 sps (provides margin and higher resolution through oversampling)

SAR ADC Architecture

Successive Approximation Register ADCs are the dominant architecture in microcontroller ADC peripherals and stand-alone ADCs up to ~18 bits at moderate sample rates. The SAR converter works as follows:

1. The sample-and-hold circuit captures the input voltage at the sampling instant.
2. The comparator and DAC perform a binary search: set the MSB, compare Vin to DAC output, decide 0 or 1, move to the next bit.
3. After n comparisons, the n-bit result is complete.
4. Total conversion time: n clock cycles (plus a few overhead cycles).

A 12-bit SAR ADC with a 20 MHz ADC clock completes a conversion in approximately 12 / 20 MHz = 600 ns — capable of around 1 Msps continuous throughput.

SAR ADC in MCUs: Most ARM Cortex-M MCUs include 12-bit SAR ADCs. The STM32 series offers 12-bit ADCs at up to ~2.4 Msps per channel; the nRF52 series offers 12-bit ADCs at up to 200 ksps.

Key considerations for MCU ADC use:

• AVDD decoupling: The ADC's analog supply needs separate decoupling (100 nF + 10 µF) from the digital supply. Many MCUs have separate AVDD pins; connect AVDD through a 10 Ω resistor or ferrite bead from VDD.
• VREF selection: The ADC accuracy is only as good as its reference voltage. The internal reference in most MCUs has ±1–3% accuracy. For better accuracy, use an external precision voltage reference (such as the REF3030 for 3.0V reference with ±0.1% accuracy).
• Source impedance: The sample-and-hold capacitor (typically 2–8 pF) must charge through the source resistance within the sampling time. The STM32 datasheet specifies a maximum recommended source impedance of about 50 kΩ for a 1.5-cycle sampling time; lower sampling times require much lower source impedance.

Sigma-Delta ADC Architecture

Sigma-delta ADCs trade sample rate for resolution. They use a 1-bit (or few-bit) quantiser running at a very high oversampling ratio (64×–4096× the output data rate), combined with noise shaping (which pushes quantisation noise to high frequencies) and digital decimation filtering (which removes the high-frequency noise and reduces the data rate back to the desired output rate).

The result is 16–24 bit effective resolution at output data rates from a few samples per second up to ~100 ksps. This makes sigma-delta ADCs the right choice for:

• Precision weigh scales (load cells, 24-bit, 10–80 sps)
• Thermocouple measurement (24-bit, 1–15 sps — with cold-junction compensation IC)
• Audio recording and playback (24-bit, 44.1–192 ksps)
• Energy metering (24-bit, 4 ksps)

Sigma-delta ADCs have high output latency due to the decimation filter's group delay. For a single conversion, the latency may be 10–100 ms. They cannot track fast-changing inputs cleanly. Use SAR for speed; use sigma-delta for resolution.

Anti-Aliasing Filter Design

For most embedded ADC applications, a simple single-pole RC low-pass filter at the ADC input is adequate. The RC filter also limits the source impedance that the ADC sample-and-hold capacitor sees:

R_filter in series with input
C_filter from input to GND
Cutoff: f_c = 1 / (2π × R × C)

Typical values: R = 100–1 kΩ, C = 100 nF → f_c ≈ 1.6 kHz.

For the MCU ADC, this also limits source impedance: at low frequencies, the capacitor dominates and the source impedance seen by the ADC is primarily R_filter, which is easy to keep under the datasheet limit.

For precision applications, a Sallen-Key or MFB active low-pass filter driven by an op-amp provides steeper rolloff and lower output impedance, at the cost of an op-amp stage.

For the complementary operation — converting a digital value back to an analog voltage — see what is a DAC?. ADC and DAC share the same resolution, reference voltage, and output buffering concepts, but serve opposite roles in a signal chain.

For hardware design of ADC front ends, sensor acquisition circuits, and precision measurement systems in embedded products, Zeus Design's engineering team handles the complete analog and digital design — contact Zeus Design.

Design Considerations

• Decouple AVDD separately from digital VDD. The ADC analog supply is sensitive to switching noise from digital logic. Use a ferrite bead or 10 Ω resistor in series from VDD to AVDD, then decouple AVDD locally with 100 nF + 10 µF. Many MCU layouts fail pre-compliance EMC testing because AVDD shares decoupling with the noisy digital supply.
• Use oversampling for effectively higher resolution without changing hardware. For a 12-bit ADC, averaging 16 samples increases effective resolution to 14 bits (4× oversampling = 1 additional bit). For n extra bits, average 4ⁿ samples. This is valid when the noise on the input is random and not correlated with the sampling rate.
• Buffer high-impedance sensors before the ADC input. Sensors such as thermistors (10 kΩ–100 kΩ depending on temperature) can exceed the ADC's maximum source impedance. Add a unity-gain op-amp follower between the sensor and the ADC input. This also provides a convenient place to add the anti-aliasing filter in the feedback network.
• Avoid routing digital signals adjacent to ADC input traces. MCU clock lines and GPIO switching currents couple capacitively into nearby traces. Keep ADC input traces away from high-frequency digital signals; route them close to the ground plane and keep them short.

Common Mistakes

• Neglecting the anti-aliasing filter. Without a low-pass filter before the ADC, high-frequency noise and interference fold back into the signal band. In an EMC-critical environment, a board without an anti-aliasing filter will pass RF noise directly into the ADC reading as DC offset and measurement noise.
• Applying more voltage to the ADC input than Vref. ADC inputs are clamped to Vref and GND with protection diodes. Exceeding Vref turns on the clamp diode and injects current into the reference supply, corrupting other ADC channels and potentially damaging the IC. Always ensure the input voltage is within [0, Vref] at all times.
• Sharing ADC reference with digital supply without isolation. If Vref is taken directly from the 3.3V digital supply without filtering, every switching event in the digital logic appears in the reference and adds directly to the ADC output. Use a separate low-dropout regulator, a precision reference IC, or at minimum a well-filtered supply node for Vref.
• Expecting 12-bit accuracy from the MCU's internal reference. Internal voltage references in microcontrollers typically have ±1–3% initial accuracy plus temperature drift. A 3% error on a 3.3V reference gives a reference voltage anywhere from 3.20V to 3.40V, which introduces up to 3% systematic error on every measurement. For accuracy-critical designs, use an external precision reference IC.