Electronics Design AUHow Do You Design Power Sequencing for a Multi-Rail Board?
Last updated 10 July 2026 · 8 min read
Direct Answer
Power sequencing is the deliberate control of the order and timing in which a board's multiple supply rails power up (and, just as importantly, power down), required whenever a device — an FPGA, a modern SoC/processor, DDR memory, or certain analog/mixed-signal ICs — specifies that one rail must reach its target voltage before another is allowed to rise, or that the gap between rails must stay within a defined maximum time. Three implementation approaches cover the large majority of designs: a dedicated power sequencer/supervisor IC (the most flexible and diagnosable option, and the standard choice for FPGAs and complex SoCs with several sequencing requirements); power-good daisy-chaining, where each regulator's enable pin is driven by the previous regulator's power-good output, creating a simple hardware-only cascade; and RC-delay enable chains, where a resistor-capacitor network on each regulator's enable pin creates a fixed, non-adjustable startup delay. Getting sequencing wrong doesn't always damage the device outright — on many parts it causes the device to fail to configure, latch up, or draw excess current, and the failure can be intermittent enough to pass a quick bench test and then fail in the field as component tolerances shift the exact timing.
Detailed Explanation
Power sequencing is easy to underestimate on a board that "just" has a few regulators, because each individual regulator's own design (output voltage accuracy, load transient response, soft-start ramp — see linear vs switching regulator) can be entirely correct while the relationship between rails is still wrong. The requirement doesn't come from the regulators themselves; it comes from downstream devices — FPGAs, many application processors, DDR memory interfaces, and some analog/mixed-signal ICs — that specify how their multiple internal supply domains must be powered relative to each other.
This is a different problem from hot-swap and inrush current limiting, which controls how fast a single rail's current ramps during turn-on. Sequencing controls the relative order and timing between multiple rails — a board can have perfectly controlled inrush on every individual rail and still violate a device's sequencing requirement if the rails aren't also correctly ordered relative to each other.
Why Devices Require a Specific Power-Up Order
A modern FPGA is the clearest example: it has separate internal supply domains — core logic voltage (VCCINT), auxiliary voltage (VCCAUX), and one or more I/O bank voltages (VCCO), plus a separate termination voltage (VTT) if the design includes DDR memory. These domains use different transistor geometries and serve different internal circuits, and many FPGA families require the core voltage to reach its target before (or no more than a specified delay after) the I/O voltages rise. Powering the I/O banks before the core logic is stable can forward-bias internal ESD structures between domains, draw excessive current through paths that were never designed to conduct in that direction, or in some cases cause the specific latch-up failure mode the sequencing requirement exists to prevent.
DDR memory interfaces add their own requirement: the VTT termination voltage (nominally half of VDDQ, used to terminate the DDR bus) typically must track the DDR I/O supply within a specified tolerance and timing window throughout power-up, power-down, and normal operation — not just satisfy a one-time ordering check at startup.
Sequencing Implementation Approaches
Dedicated power sequencer/supervisor IC. A purpose-built sequencer (for example, TI's UCD90xxx family or similar parts from other analog vendors) monitors multiple rails' voltages and drives each regulator's enable pin according to a configured sequence — often with margin monitoring, fault reporting, and the ability to sequence both power-up and power-down independently. This is the most flexible option and the standard choice for FPGAs and SoCs with several rails and a documented, sometimes intricate, sequencing requirement. It's also the easiest to diagnose during bring-up, since many sequencer ICs report exactly which rail failed to reach its target within the expected window.
Power-good daisy chaining. Each regulator's enable pin is wired to the previous regulator's power-good (PG) output, creating a simple hardware cascade: rail 2 doesn't start ramping until rail 1's regulator asserts power-good. This requires no separate sequencer IC and adds minimal cost, but it only enforces ordering (rail 2 waits for rail 1), not a specific timing window between them, and it typically doesn't provide an independently controllable power-down sequence — many regulators drop their enable and power-good simultaneously on shutdown rather than in a controlled reverse order.
RC-delay enable chains. A resistor-capacitor network on each regulator's enable pin creates a fixed startup delay, staggering when each rail begins ramping relative to a common enable signal. This is the lowest-cost option but the least robust: the delay is fixed at design time (not adaptive to the actual rise time of the preceding rail, which shifts with load and component tolerance), doesn't verify the preceding rail actually reached its target voltage before releasing the next one, and provides no fault reporting if a rail fails to come up.
| Approach | Enforces order | Enforces timing window | Power-down sequencing | Fault reporting | Typical use case |
|---|---|---|---|---|---|
| Sequencer/supervisor IC | Yes | Yes, precisely | Yes, independently configurable | Yes | FPGAs, complex SoCs, safety-relevant designs |
| Power-good daisy chain | Yes | No (waits for PG, not a specific delta) | Usually no | Limited | Moderate rail counts, simpler timing requirements |
| RC-delay enable chain | Approximately (fixed delay only) | No (fixed, not adaptive) | No | No | Low rail count, cost-sensitive, generous timing margin |
DDR VTT: A Sequencing Requirement That Never Really Ends
Unlike a one-time power-up ordering check, DDR's VTT termination voltage must continue tracking VDDQ/2 throughout normal operation, not just during the initial power-up window — this is usually handled by a dedicated DDR termination regulator IC designed specifically to track its reference input continuously, rather than a general-purpose sequencer output. Confirm the DDR termination solution is rated for continuous tracking, not just a startup ramp, when selecting the termination regulator for a DDR-based design.
Practical Examples
An FPGA-based industrial controller uses a UCD90124-class sequencer to bring up VCCINT first, hold until it crosses a monitored threshold, then release VCCAUX and the VCCO banks together within the FPGA vendor's specified maximum delay window. The sequencer also reverses the order on controlled shutdown and latches a fault flag (readable by the host MCU over I2C) if any rail fails to reach its target within the expected time — turning what would otherwise be a silent configuration failure into a diagnosable fault reported at the system level.
A cost-sensitive consumer product with a simple two-rail requirement (a 1.8V core rail that must precede a 3.3V I/O rail by a modest, generously-toleranced delay) uses a power-good daisy chain instead of a full sequencer IC: the 3.3V regulator's enable pin is tied to the 1.8V regulator's power-good output. This satisfies the ordering requirement at minimal cost, though it provides no independent power-down sequencing — accepted as a reasonable trade-off after confirming the device's power-down requirements are not similarly strict.
Design Considerations
- Read the specific device's power-up (and power-down) sequencing requirements directly from its datasheet or configuration user guide before choosing an implementation approach — the required precision (a loose ordering requirement vs a tight timing window) determines whether a low-cost RC-delay chain is adequate or a full sequencer IC is actually necessary.
- Verify power-down sequencing as a separate requirement from power-up, not an assumption that reversing power-up automatically satisfies it — see the FAQ above; many low-cost sequencing methods control only the power-up direction.
- Choose a sequencer IC with fault reporting for any design where silent sequencing failure would be hard to diagnose in the field — an FPGA that fails to configure due to a marginal sequencing violation can look identical, from the outside, to a configuration bitstream problem or an unrelated hardware fault, unless the sequencer itself reports which rail was the actual cause.
- Re-verify sequencing timing across the full worst-case tolerance range of every component involved, not just with nominal-value parts on the bench — a sequencing design that passes on prototype units built from parts near the centre of their tolerance can still violate the requirement once production units span the full specified tolerance range.
- Zeus Design's electronics design team designs and verifies power sequencing for FPGA, SoC, and multi-rail embedded products, including sequencer IC selection and bring-up verification.
Common Mistakes
- Assuming a board with multiple rails automatically needs a full sequencer IC. Sequencing is only required where a specific device demands it — check the datasheet before adding sequencing complexity a design doesn't actually need (see the FAQ above).
- Designing power-up sequencing while leaving power-down unaddressed. A device's shutdown sequencing requirement is a genuinely separate item from its power-up requirement and is frequently missed because it's easy to assume the power-up design "just reverses" on shutdown.
- Using a fixed RC-delay chain for a device with a tight timing-window requirement, rather than a genuine ordering-plus-timing requirement — a fixed delay calculated against nominal component values doesn't adapt to the actual rise time of the preceding rail under real load and tolerance conditions.
- Validating sequencing only with nominal-value bench parts. A sequencing design that appears correct on the bench can still fail in production once regulator soft-start times, RC component tolerances, or supervisor threshold accuracy vary across their full specified range.
- Overlooking DDR VTT's continuous tracking requirement and treating it like a one-time power-up ordering item rather than a rail that must keep tracking VDDQ throughout normal operation, not just at startup.
Frequently Asked Questions
- Does every multi-rail board need active power sequencing?
- No — sequencing is only required when a specific device on the board has a documented power-up ordering or timing requirement, not simply because a board has more than one supply rail. Many boards with multiple independent rails (for example, a digital 3.3V rail and a completely separate analog sensor supply with no shared device dependency) have no sequencing requirement at all, and each regulator can free-run independently. The requirement comes from the device datasheet — FPGAs, many SoCs and application processors, and DDR memory interfaces are the parts most likely to specify a sequencing order or maximum inter-rail delay; always check the specific device's power-up requirements section before assuming sequencing is or isn't needed.
- What happens if I violate an FPGA's power sequencing requirement?
- The specific consequence depends on the FPGA family and which rails are violated, so always check the specific device's configuration user guide rather than assuming a generic outcome — but common failure modes include the device failing to complete configuration (it powers up but never loads its bitstream, often with a configuration-failure status pin asserted), excessive current draw during the violation window that can trip the supply's own current limit, or in the worst case, latch-up that draws sustained excess current until power is removed. Because the exact failure often depends on how far outside the specified window the violation is, a marginal sequencing violation can appear to work in bench testing (where component tolerances happen to land in a forgiving range) and then fail once the same design is built at volume with parts spread across their normal tolerance range.
- Do rails need to be sequenced on power-down too, not just power-up?
- For many devices, yes — the power-down (shutdown) sequence often has its own requirement, sometimes the same order as power-up and sometimes reversed, and it's a commonly overlooked half of the sequencing design. A sequencer IC handling only power-up ordering while leaving power-down uncontrolled can still violate the device's requirements during every power-loss event or controlled shutdown. Check the specific device's datasheet for power-down sequencing requirements as a distinct item from power-up requirements, and verify the chosen sequencing method (sequencer IC, power-good daisy chain, or RC delay) actually controls both directions — a simple RC delay chain, for example, does not inherently guarantee a controlled power-down order, only a controlled power-up ramp.
References
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