What Is Ethernet?

Detailed Explanation

Ethernet provides reliable wired connectivity in situations where wireless is unsuitable — industrial environments with RF interference, applications requiring low latency and deterministic timing, safety-critical systems requiring a cable-tethered connection, or high-throughput data transfers that exceed what Wi-Fi can provide reliably. Understanding the MAC/PHY split and the MAC-PHY interface is essential for designing embedded systems with Ethernet. When the design needs only on-board peripheral communication rather than IP networking, SPI, I2C, and UART are substantially simpler to implement; Ethernet's added complexity is justified by cable-run length, throughput, or the need for TCP/IP-based connectivity.

The MAC/PHY split

IEEE 802.3 defines Ethernet in two distinct layers:

PHY (Physical Layer transceiver) — handles the analogue side: transmitting and receiving the encoded signal on the twisted-pair cable. For 100BASE-TX, this is 4B/5B encoding and MLT-3 line code on two pairs. The PHY also handles auto-negotiation (agreeing speed and duplex with the link partner), signal equalization, and clock recovery. A separate PHY IC is almost always required because the analogue circuitry required for cable driving is incompatible with digital MCU fabrication processes.

MAC (Media Access Control) — handles the digital side: framing (preamble, destination address, source address, EtherType/length, data, FCS CRC), CSMA/CD collision detection (for half-duplex, now rare), and the interface to the system bus (DMA, memory). The MAC is commonly integrated into the microcontroller on STM32F4/F7/H7, i.MX, and similar application-class parts.

MAC-PHY interfaces

MII (Media Independent Interface): 18 signals, 4-bit data paths, 25 MHz reference clock for 100 Mbit/s. Original standard; still used but being superseded by RMII in new designs.

RMII (Reduced MII): 10 signals (TX data 2-bit, RX data 2-bit, TX enable, CRS/DV, RX error, reference clock). All signals run at 50 MHz. The MCU or an external oscillator provides the 50 MHz RMII reference clock. RMII is the most common interface for embedded Ethernet PHYs in 2024.

RGMII (Reduced Gigabit MII): 4-bit data path with double-data-rate clocking at 125 MHz for 1 Gbit/s. Requires careful PCB layout for signal integrity — trace length matching between the 4 data lines and the reference clock is critical.

MDIO/MDC (Management Data I/O / Management Data Clock): a two-wire serial interface separate from the data path, used to read and write PHY registers for configuration (speed, duplex, power, autonegotiation control), status reading (link state, error counters), and the PHY's extended register sets. The MAC firmware accesses the PHY over MDIO/MDC during initialisation and for link status monitoring.

Common embedded Ethernet PHY ICs

TCP/IP stack

Ethernet provides a Layer 2 (data link) transport. For IP networking, a TCP/IP stack runs above the MAC layer:

• lwIP (lightweight IP): the dominant open-source TCP/IP stack for embedded systems (MCUs). Used with STM32 HAL, NXP ENET, and similar. Provides TCP, UDP, DHCP, DNS, HTTP, and MQTT clients and servers. Runs with or without an RTOS.
• FreeRTOS+TCP: a thread-safe TCP/IP stack designed for use with FreeRTOS. Similar feature set to lwIP.
• Bare-metal stacks: simpler stacks (uIP, picoTCP) for very resource-constrained MCUs (under 16 KB RAM).
• Linux networking stack: on Yocto/Buildroot Linux embedded systems (i.MX, Raspberry Pi), the full Linux TCP/IP stack is available with standard BSD socket API.

Practical Examples

An industrial machine controller uses an STM32H743 with on-chip Ethernet MAC connected to a LAN8720A PHY over RMII. The lwIP stack provides a Modbus TCP server for the SCADA system to read sensor values and write setpoints, and an MQTT client to publish production statistics to an AWS IoT Core endpoint. Ethernet provides the deterministic low-latency connectivity required for the SCADA interface; the MQTT data path uses the same physical connection.

A test and measurement instrument (a precision impedance analyser) uses an RJ45 Ethernet port for remote control via a custom REST API and for streaming measurement data at 100 Mbit/s throughput. The instrument's ARM Cortex-A processor runs embedded Linux with the full Linux networking stack, providing standard socket APIs for the application firmware.

Design Considerations

• Magnetics: Ethernet requires transformer-coupled magnetics (isolation transformers + common-mode chokes) between the PHY and the RJ45 connector. Most RJ45 connectors with integrated magnetics (MagJack or RJ45+) include these on the connector PCB. Confirm the magnetics match the PHY's impedance specification (typically 1:1 transformer ratio for 10/100BASE-TX).
• PCB layout for Ethernet: the differential pairs (TX+/TX−, RX+/RX−) must be routed with matched trace lengths (within 50 mil between pair), controlled differential impedance (typically 100 Ω differential), and continuous ground return beneath the traces. Keep Ethernet traces away from noisy power converters. See PCB ground plane design for guidance on maintaining ground reference integrity.
• 50 MHz RMII clock source: the RMII 50 MHz reference clock can come from the MCU (requires an accurate 50 MHz output from a PLL) or from an external crystal oscillator on the PHY (check the PHY datasheet for which mode is supported). Many LAN8720A designs use a 25 MHz crystal on the PHY with the PHY internally generating the 50 MHz RMII clock — verify the PHY's REFCLK configuration mode in its strap pins.
• ESD protection: Ethernet lines at the connector are exposed to high-voltage ESD events. Add a bidirectional TVS protection array (typically 0.5 pF or lower capacitance) on the RJ45 side of the magnetics. The magnetics themselves provide isolation but not sufficient ESD clamping.

Common Mistakes

• Incorrect PHY strap pin configuration: most PHY ICs use dedicated pins sampled at power-on to configure RMII vs MII mode, PHY address (for MDIO), and speed/duplex default. If these pins are left floating or incorrectly tied, the PHY boots in the wrong mode and the MAC-PHY link does not establish. Always define strap pin states explicitly in the schematic.
• Missing or incorrect Ethernet magnetics: driving the RJ45 connector directly from the PHY without isolation magnetics violates 802.3 specifications, creates EMC problems, and may damage the PHY from ESD. Always use integrated magnetics (integrated into the connector or as a discrete transformer module).
• Incorrect RMII reference clock routing: the 50 MHz RMII reference clock is a critical, high-speed clock signal. It must be routed to all RMII devices (both MAC and PHY) with a controlled-impedance trace and minimal stub length. Daisy-chaining through a long stub introduces timing skew that prevents the RMII link from training.
• lwIP thread safety on FreeRTOS: lwIP in non-OS mode is not thread-safe. If multiple RTOS tasks call lwIP functions concurrently without a mutex, memory corruption results. Use FreeRTOS+TCP or configure lwIP with RTOS integration and a single network task.