What Is Controlled Impedance PCB Design, and Why It Matters?

Detailed Explanation

Every PCB trace has a characteristic impedance determined by its width, the copper thickness, the dielectric material and thickness separating it from its reference plane, and (for differential pairs) the spacing between the two traces. At low frequencies this is largely irrelevant — the trace just carries a signal. At the frequencies and edge rates typical of high-speed digital and RF signals, a trace behaves as a transmission line, and a mismatch between its impedance and the impedance the driving or receiving circuit expects causes signal reflections that degrade signal quality, sometimes badly enough to cause functional failures.

Controlled impedance design means deliberately calculating trace geometry — using the stack-up's known dielectric properties — to hit a specific target impedance, then verifying the result, typically with a fabrication house's impedance test coupon, since manufacturing tolerances on dielectric thickness and etch width both shift the actual built impedance slightly from the calculated target.

Practical Examples

A USB 2.0 differential pair needs to maintain approximately 90Ω differential impedance along its entire routed length. That requirement constrains trace width, the spacing between the pair's two traces, and how far the pair sits from its reference plane — all of which were effectively fixed the moment the stack-up was chosen, since the dielectric thickness above the reference plane is one of the calculation's key inputs.

A single-ended RF trace feeding an antenna typically targets 50Ω, calculated from trace width and the stack-up's dielectric height above its reference plane using a microstrip or stripline impedance formula (most EDA tools include a built-in calculator for this) — and any via placed in that trace introduces a small impedance discontinuity that matters more as frequency increases.

A MIPI DSI display interface routes differential data lanes at 100Ω — each D-PHY lane is a differential pair capable of 1.5 Gbps in high-speed mode, where any impedance mismatch produces reflections that corrupt pixel data. Differential pair trace length must be matched both within each pair (+ and − conductors) and across all lanes, and the target impedance is set by the same stack-up geometry chosen before routing begins.

A 100BASE-TX Ethernet differential pair also targets 100Ω differential — the transmit (TX+/TX−) and receive (RX+/RX−) pairs between the PHY IC and RJ45 magnetics must be routed at 100Ω controlled impedance with matched intra-pair trace lengths. At Gigabit Ethernet speeds (1000BASE-T), signalling frequency increases and the as-built impedance tolerance becomes a harder constraint.

Design Considerations

• Fix the stack-up before routing any impedance-critical net — dielectric thickness and reference-plane distance are direct inputs to the impedance calculation, and changing them after routing means re-deriving trace widths from scratch.
• Use your fab house's actual dielectric constant and copper thickness values, not generic textbook numbers, since manufacturing tolerances and material substitutions both shift the calculated result.
• Request impedance test coupons from the fab house for anything genuinely impedance-critical — calculation gets you close; a measured test coupon confirms the as-built board actually hits the target.
• Minimise vias and layer changes on impedance-controlled nets, and where unavoidable, understand each one introduces a small discontinuity — see types of PCB vias for how via choice affects this.
• Impedance-critical designs: High-speed and RF boards where controlled impedance is a hard requirement benefit from working with a specialist PCB design team experienced in coordinating trace geometry, stack-up, and fab-house impedance test coupons.

Common Mistakes

• Routing a high-speed or RF trace at an arbitrary width and only checking impedance after the fact, rather than calculating the required width from the stack-up before routing.
• Using a generic or assumed dielectric constant instead of the fab house's actual material data, producing a calculated impedance that doesn't match the as-built board.
• Treating impedance control as relevant only to RF work, then discovering a high-speed digital interface's signal integrity problems trace back to unmanaged impedance.
• Skipping impedance test coupons on a board where it actually matters, finding out the target was missed only after the board fails in test or the field.