What Is JTAG?

Detailed Explanation

JTAG emerged in the late 1980s from the Joint Test Action Group, an industry consortium addressing a specific manufacturing test problem: as PCB densities increased and component pitch decreased, traditional bed-of-nails test fixtures could no longer physically probe every node on a board. The IEEE 1149.1 standard that emerged defined the boundary scan architecture and the JTAG serial interface used to drive it.

Over time, IC vendors co-opted the JTAG hardware interface (the same TAP state machine and four-wire bus) for a second purpose: in-circuit debugging and programming of microcontrollers, FPGAs, CPLDs, and DSPs. This is the role most embedded engineers encounter JTAG in — not boundary scan testing, but device debug and programming.

The TAP state machine

Every JTAG-capable IC includes a TAP (Test Access Port) controller — a 16-state state machine clocked by TCK and navigated by the TMS input. The key states:

• Test-Logic-Reset: initial state; TAP is in a known idle state
• Shift-DR: shift data bits through the selected data register (boundary scan, ID code, debug access port, etc.)
• Shift-IR: shift a new instruction into the instruction register, selecting which data register is active
• Update-DR: capture the shifted data and apply it to the selected register's outputs

The host (debug probe) drives TMS to navigate through states and TDI to shift data in; TDO carries data out. TCK provides the timing.

JTAG for microcontroller debugging

On ARM Cortex-M microcontrollers, JTAG connects to the CoreSight debug infrastructure — the same infrastructure accessed by SWD. The JTAG interface connects to the DAP (Debug Access Port), which provides:

• AHB-AP (AHB Access Port): access to the MCU memory bus for reading/writing RAM, flash, and peripheral registers
• Halting control: stopping the CPU at breakpoints and single-stepping instructions
• Core register access: reading/writing CPU registers (PC, SP, LR, general-purpose registers)
• ITM/ETM trace: instruction trace and data trace via optional SWO output

Standard ARM JTAG headers:

• ARM 20-pin (0.1 inch): the legacy connector, physically large, found on older eval boards
• ARM 10-pin Cortex Debug Connector (0.05 inch, 1.27 mm pitch): compact header standard for modern embedded designs, provides TCK, TMS, TDI, TDO, nSRST, GND, and VCC reference

JTAG for FPGA configuration

FPGAs are routinely programmed and debugged over JTAG. The FPGA bitstream is shifted into the device via the JTAG TDI/TDO path; in boundary scan mode, the FPGA's IO pins can be driven and sampled for board-level testing. FPGA vendors provide JTAG programming tools: Intel/Altera Quartus Programmer, AMD/Xilinx Vivado Hardware Manager. The JTAG interface is also used for FPGA in-system logic analysis (SignalTap on Intel, ILA on Xilinx) without requiring external logic analyser connections.

JTAG chain: multiple devices

Multiple JTAG-capable ICs can be connected in a chain: TDO of the first device connects to TDI of the second, TDO of the second to TDI of the third, and so on. TCK and TMS are shared across all devices. The host sends the appropriate instruction length to navigate each device independently, or shifts through all devices to test the entire chain at once. JTAG chains are common in automotive and industrial boards where multiple FPGAs, CPLDs, or mixed-signal ICs share a single JTAG connector.

Practical Examples

During PCB bring-up of an STM32F4 board, the engineer connects a J-Link debug probe to the 10-pin Cortex Debug header. Using Ozone (J-Link's debug GUI), they set a breakpoint in main(), start the target, and verify the CPU halts correctly. Memory view in Ozone shows the peripheral register values — confirming the RCC clock tree is configured correctly and the GPIOA ODR register toggles when the LED control code runs. This is all done via JTAG, though the J-Link defaults to SWD if available.

A telecom line card with three FPGAs and two CPLDs uses a daisy-chained JTAG connection to a single 14-pin JTAG header at the board edge. Factory JTAG test software (JTAG Technologies ProVision) performs boundary scan on the assembled board, checking for solder defects on BGAs before powering the board and programming the FPGAs via the same chain.

See how to debug embedded firmware for a practical guide to using JTAG and SWD debug probes in an embedded development workflow.

Design Considerations

• JTAG or SWD for Cortex-M debug: both access identical debug infrastructure. Choose SWD when pins are scarce (two wires vs four). Use JTAG when you need boundary scan, when connecting multiple devices in a JTAG chain, or when JTAG-only debug probes are available in the lab.
• TCK frequency: the maximum TCK frequency is limited by the target MCU's JTAG implementation and PCB signal integrity. Most Cortex-M targets support up to 10–20 MHz TCK; higher frequencies may produce errors due to propagation delay or capacitive loading on the JTAG lines. Start at a lower frequency (1–4 MHz) during bring-up and increase after confirming reliable communication.
• JTAG connector placement: place the JTAG/SWD connector at the board edge with a clear approach path for the probe cable. The connector should be accessible with the board in its housing if possible, as embedded debug is often needed during final integration. See PCB bring-up checklist for a systematic approach to first-time hardware bring-up.
• Pull-up resistors on JTAG lines: TMS should have a pull-up resistor (typically 10 kΩ) to VCC to ensure the TAP state machine defaults to Test-Logic-Reset when no probe is connected. TDI can float safely in most implementations, but adding a pull-up ensures consistent behaviour. TCK and TDO typically require no pull resistors.

Common Mistakes

• Incorrect JTAG connector pinout: JTAG headers have multiple incompatible pinout standards (ARM 20-pin, ARM 10-pin Cortex, MIPI 10-pin, MIPI 20-pin). Verify the exact pinout from the probe vendor's documentation and the MCU/FPGA vendor's evaluation board reference design — never assume connector compatibility without checking.
• JTAG signals sharing GPIO pins with other functions: on STM32, JTAG pins (PA13/PA14/PA15/PB3/PB4) are the default JTAG/SWD pins and are configured as JTAG debug pins at reset. If these pins are needed for other functions (e.g. SPI), the JTAG/SWD interface must be disabled in firmware (AFIO_MAPR on STM32F1, or appropriate debug port disable sequence). Failing to do this causes the SPI port to not work and JTAG to conflict with the SPI device.
• Forgetting nSRST in reset scenarios: some debug sequences require asserting the system reset (nSRST) to halt the CPU immediately at reset before any code runs. If nSRST is not connected to the JTAG header, the debug probe cannot perform reset-halt sequences, making debugging of early startup code difficult.
• TCK too fast for the target or cable length: at 20+ MHz TCK frequencies, propagation delay and capacitive loading on the JTAG cable can cause marginal timing. Use adaptive clocking (RTCK) or reduce TCK to a frequency the target reliably supports.