What Is SWD (Serial Wire Debug)?

Detailed Explanation

SWD was introduced by ARM as part of the CoreSight debug and trace architecture to provide a lower-pin-count alternative to JTAG for debugging ARM Cortex-M microcontrollers. As embedded designs grew increasingly pin-constrained — particularly in small form-factor IoT and wearable devices — the four pins required by JTAG became a meaningful hardware cost. SWD reduces this to two pins (plus power and ground) without sacrificing any debugging capability.

SWD protocol fundamentals

SWD uses two signals:

• SWDCLK — clock driven by the debug probe (host)
• SWDIO — bidirectional data line, driven by the probe during command phases and by the target during response phases

Unlike JTAG's separate TDI and TDO paths, SWDIO multiplexes both directions on a single line. The probe drives SWDIO for request packets; the target drives SWDIO for acknowledgement and response packets; a brief turnaround period between each direction change prevents both sides from driving simultaneously.

A SWD transaction consists of:

1. Request packet (8 bits, host → target): start bit, AP/DP select, R/W direction, 2-bit address, odd parity, stop bit, park bit
2. Turnaround (1 clock cycle idle)
3. Acknowledgement (3 bits, target → host): OK/WAIT/FAULT
4. Data phase (32 data bits + 1 parity bit, direction depends on R/W)
5. Turnaround (1 clock cycle idle)

This protocol accesses two types of registers:

• DP (Debug Port) registers: directly accessible via SWD — IDCODE, CTRL/STAT, SELECT, RDBUFF
• AP (Access Port) registers: accessed via the DP SELECT mechanism — the MEM-AP (memory-mapped access port) provides 32-bit read/write access to the entire MCU address space (RAM, flash, peripheral registers)

ARM CoreSight debug infrastructure

SWD connects to the ARM CoreSight DAP (Debug Access Port), which provides access to the Cortex-M's internal debug components:

• Halt and step control: the CPU can be halted at any instruction, single-stepped, and resumed. Registers (PC, SP, LR, r0–r15, XPSR) can be read and written while halted.
• Breakpoints: hardware breakpoints (FPB — Flash Patch and Breakpoint Unit) allow halting when execution reaches a specific address (typically 4–8 hardware breakpoints on Cortex-M0 to M7).
• Watchpoints: data watchpoints (DWT — Data Watchpoint and Trace Unit) halt the CPU when a specific memory address is read, written, or both — essential for tracking memory corruption bugs.
• ITM trace (via SWO): the Instrumentation Trace Macrocell supports printf-style debug output via stimulus ports without halting the CPU. SWO carries ITM packets at up to several Mbit/s; the debug probe captures and decodes them.

SWJ-DP: combined JTAG and SWD

Most ARM microcontrollers implement SWJ-DP (Serial Wire JTAG Debug Port), which supports both JTAG and SWD on the same physical pins:

• SWDIO / TMS share a pin
• SWDCLK / TCK share a pin
• JTAG-only TDI and TDO are additional optional pins

The debug probe selects the protocol by sending a predefined switching sequence. JTAG-to-SWD switching: >50 clock cycles with SWDIO high, then 0xE79E (16-bit sequence), then >50 clock cycles with SWDIO high, then line reset. Most probes perform this automatically during connection.

Debug connectors for SWD

ARM 10-pin Cortex Debug Connector (1.27 mm pitch / 0.05 inch): The compact standard for modern embedded designs, fitting in minimal board space. Pinout: VCC reference, SWDIO, GND, SWDCLK, GND, SWO, KEY (no pin), nRESET, GND Detect (optional), nTRST (optional).

ARM 20-pin (2.54 mm / 0.1 inch): The legacy connector, larger and less common in new designs, but compatible with older J-Link cables and ST-Link V2 adapters.

TagConnect (TC2030-CTX): A spring-contact footprint requiring no physical connector — the probe clips directly onto pads on the PCB. Eliminates connector cost and saves board space for production hardware where the debug port is accessed only during testing.

Practical Examples

An STM32L4 IoT sensor board uses a 10-pin ARM Cortex Debug header for development and a TagConnect TC2030 pads for production factory programming (connecting via ST-Link). During development, a J-Link probe connects to the 10-pin header; the SWD clock runs at 4 MHz; the SWO pin carries ITM trace output at 4 Mbit/s for real-time profiling of the sensor sampling and transmission timing. See how to debug embedded firmware for a practical workflow using SWD in a development environment.

When the STM32 DFU bootloader jump fails to re-enumerate on USB, connecting a J-Link probe via SWD allows the engineer to halt the CPU immediately after reset and step through the bootloader entry code — diagnosing the exact failure point without any console output. See STM32 DFU bootloader for more on this specific scenario.

Design Considerations

• Minimum SWD connector: for space-constrained designs, the TagConnect TC2030-CTX provides factory programming with no PCB connector at all — just six pads. For development boards where a physical connector is acceptable, the 10-pin ARM Cortex connector is the minimum practical choice.
• SWO pin for trace: decide early whether to include the SWO pin in the debug connector and MCU pinout. SWO requires the SWO/ITM-capable pin to be available (not used for another function) and routed to the debug header. ITM trace is extremely valuable for production debugging of timing issues that cannot be observed with breakpoints; including SWO from the start costs nothing at design time.
• SWDCLK and SWDIO pull resistors: SWDIO requires a pull-up resistor (typically 100 kΩ) to VCC to prevent false triggering when no probe is connected. SWDCLK should have a pull-down (typically 100 kΩ) to prevent spurious clocking. These resistors are required by the ARM SWD specification and should not be omitted in cost-reduction exercises.
• nRESET connection: the debug probe uses nRESET (the MCU system reset) to perform reset-halt sequences — halting the CPU at the very first instruction before any code runs. If nRESET is not connected to the debug header, the probe cannot perform a reset-halt, making debugging of startup code and pre-main initialisation impossible.
• Lock-out risk: some MCUs allow the SWD/JTAG debug interface to be disabled in firmware as a security feature (e.g. STM32 RDPP2 readout protection). Activating this without a recovery path can permanently brick the device. Always implement a hardware-verified recovery mechanism before enabling debug port lock-out in production firmware.

Common Mistakes

• Floating SWDIO during reset: if SWDIO is not pulled up, it floats during the MCU reset sequence. Some MCUs sample SWDIO at reset to configure boot options — a floating SWDIO can cause unexpected behaviour.
• SWDCLK sharing with a high-current output: the debug probe drives SWDCLK with its own driver. If the SWDCLK pin is connected to external circuitry that drives significant current (motor driver enable, relay), the probe may be fighting the external driver. Keep SWDCLK as a dedicated debug signal or add series resistance (100 Ω) to isolate the probe from the external load.
• Using STM32 JTAG pins (PA13/PA14) as GPIO without remapping: PA13 (SWDIO) and PA14 (SWDCLK) are the default SWD pins on STM32 and are in AF SWD mode at reset. If firmware configures these as GPIO outputs without first disabling SWD, the debug connection is lost. Always disable SWD explicitly in firmware before reconfiguring these pins; keep a copy of the firmware that re-enables SWD for recovery.
• Incorrect SWD connector orientation: the 10-pin ARM Cortex connector is designed to be shrouded with a key pin to prevent reverse insertion, but unkeyed versions are common. Connecting the probe in reverse applies power to signal lines and can damage the MCU or probe. Mark pin 1 clearly on the PCB silkscreen.