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Op-amp output oscillating at ~200 kHz — only happens when I add the anti-aliasing cap

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Original Question

Asked by fresh_grad_fern ·

Building a signal conditioning board for a resistive sensor — non-inverting amplifier stage at gain of 6 (51 kΩ / 10 kΩ feedback), running on ±5 V, OPA2134. Output goes through a 1 kΩ series resistor and a 100 nF cap to the MCU ADC input as a first-order anti-aliasing filter.

The problem: I'm seeing a ~200 kHz oscillation on the output with a constant DC input. Put the scope probe right on the OPA2134 output pin (before the 1 kΩ resistor) and the oscillation is already there. Removed the 100 nF cap, oscillation stops completely. Put it back, oscillation returns.

Got 100 nF ceramics directly on the supply pins and a 10 µF bulk cap nearby, so I don't think it's supply noise. Tried two different ICs from the same reel — same result.

The OPA2134 datasheet says it's unity-gain stable, so I assumed gain 6 would be fine. Why would a simple RC filter on the output cause this? Is this a layout problem, or is there something fundamentally wrong with the circuit?

From the knowledge baseWhat Are Inverting and Non-Inverting Op-Amp Amplifier Configurations?

3 Replies

opamp_oracle
Accepted Answer

This is capacitive load instability, and the OPA2134 is not at fault — the circuit configuration is.

Unity-gain stable doesn't mean stable with any load. It means the op-amp's internal compensation is sufficient for resistive loads at unity gain. A capacitive load adds a phase-lagging pole inside the feedback loop, and that pole consumes phase margin. When phase margin reaches zero, the amplifier oscillates instead of settling.

Here's the mechanism. The OPA2134's output stage has a real, non-zero open-loop output impedance — typically 20–80 Ω. Your 100 nF cap and that output impedance form an RC pole:

f_pole = 1 / (2π × Zo × C) ≈ 1 / (2π × 50 Ω × 100 nF) ≈ 32 kHz

The OPA2134 has a GBW of 8 MHz. At your closed-loop gain of 6, the 0 dB crossover lands around 1.3 MHz. Between 32 kHz and 1.3 MHz, that RC pole is contributing additional phase lag — approaching 80–90° by the time you hit 200 kHz. Phase margin is gone. The loop rings, then oscillates at whatever frequency the phase crosses –180°.

The 1 kΩ resistor you already have is almost the right fix — but only if you restructure where the feedback is taken. What you need is an Riso (isolation resistor) topology:

  1. Connect the feedback network (51 kΩ from output, 10 kΩ to ground) directly to the op-amp output pin — the feedback must not include the RC filter.
  2. Place a 100–200 Ω resistor (Riso) between the op-amp output and the RC filter.
  3. The 1 kΩ + 100 nF continue from after Riso to the ADC input.

With this topology, the closed loop sees only the op-amp driving a resistive Riso. The RC filter is a passive network sitting after the feedback takeoff point — its pole no longer affects loop stability. The OPA2134 settles cleanly, and the filter still functions.

One note on your filter: 1 kΩ + 100 nF is –3 dB at about 1.6 kHz. Check that cutoff against your sampling rate — the ADC explainer covers the Nyquist relationship if you want to verify the anti-aliasing margin. And for the gain and frequency context behind why this kind of instability happens, the non-inverting amplifier overview is worth re-reading with the GBW limit in mind.

gain_bandwidth_gus

opamp_oracle has the diagnosis right. One more thing to rule out while you're revising the circuit: check whether you have any capacitance from the inverting input node to ground.

A very common variant of this problem — especially if you've been following simulation tutorials — is adding a small bypass cap across the lower feedback resistor to "filter noise on the feedback divider." In simulation it often looks fine. On hardware it places a pole in the closed-loop response that eats phase margin in a way that looks almost identical to the capacitive output load problem.

If you have any cap there, remove it first. The correct way to add HF rolloff inside the loop is a small capacitor in parallel with the upper feedback resistor (51 kΩ). This forms a pole that rolls off closed-loop gain gracefully at frequency. For an 8 MHz GBW part at gain 6, something in the range of 5–10 pF across the 51 kΩ is typically enough to gain a useful margin improvement without affecting the passband.

The underlying framework here is the Bode gain-phase relationship: every pole in the loop adds –90° of phase asymptotically, and every zero recovers some. The op-amp fundamentals page covers GBW and slew rate — working through those numbers for your specific device before committing to a topology saves the kind of late discovery you've just hit.

filter_fanatic_flo

The Riso fix will sort out the oscillation. Worth flagging one thing for the longer-term design though: whether a first-order passive RC is actually enough anti-aliasing for your application.

A first-order filter at 1.6 kHz only rolls off at –20 dB/decade. If you're sampling at, say, 10 kHz, you're getting roughly 14 dB of attenuation at Nyquist (5 kHz). Whether that's sufficient depends on how much signal energy exists above Nyquist and what SNR you need at the ADC — but for precision sensor work it often isn't.

If you find you need more rolloff, a Sallen-Key second-order low-pass is the cleaner route rather than cascading more passive RC sections. The op-amp is designed into the filter topology from the start, so stability is part of the design analysis rather than something you patch afterward. You still need to watch GBW vs Q-factor (high-Q Sallen-Key stages on a bandwidth-limited op-amp will peak), but the trade-offs are explicit.

It depends entirely on what your sampling rate actually is and how much alias rejection you need — sometimes a first-order RC is fine and sometimes it isn't. Either way, knowing which situation you're in before the board spins is worth the half-hour.

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