Electronics Design AUPCB failing radiated emissions near 200 MHz on pre-compliance scan — where to start?
Asked by whateverlol88 ·
Ran our first pre-compliance EMI scan this week. Board passes CISPR 32 Class B limits cleanly below 150 MHz, but there's a clear peak at 196 MHz sitting about 6 dB over the limit. MCU is STM32F405 running at 168 MHz from an 8 MHz external crystal. We're also running a 500 kHz synchronous buck converter for the 3.3V rail.
Stackup is 4-layer with a solid ground plane on L2 and a power plane on L3. I'm trying to understand whether the 196 MHz peak is coming from the MCU clock, the SMPS, or something else entirely — and what to fix first before paying for the formal test.
3 Replies
Almost certainly a digital clock product, not the SMPS. Your 500 kHz converter's harmonics land at 500 kHz, 1 MHz, 1.5 MHz ... all well below 196 MHz. The 196 MHz peak is almost certainly related to the 168 MHz CPU clock: 168 × 7/6 = 196 MHz is a common intermodulation product from the PLL, or it could be near 168 MHz + one harmonic of the 8 MHz crystal. Either way, scope it to the MCU, not the switcher.
First thing to do before anything mechanical: enable spread-spectrum clocking on the STM32F405 PLL in CubeMX. The F4 supports centre-spread on the main PLL output, which spreads the energy in the 168 MHz harmonic across a wider bandwidth and can reduce the peak by 6–10 dB on its own, sometimes enough to bring a marginal failure under the limit. It's a firmware change, costs nothing, and takes five minutes to test.
If spread-spectrum isn't enough, the diagnostic step is a near-field H-field loop probe near the MCU versus near the crystal and versus near the SMPS section. The probe that makes the 196 MHz peak jump most when brought close identifies the dominant radiating structure. Common culprits: a long trace running from the MCU that acts as an antenna at λ/4 near 196 MHz (about 36 cm in FR4), or the crystal circuit itself if it's not guarded.
Practical layout fixes in rough priority order:
- Guard the crystal with a ground pour stitched to L2, and keep crystal traces short and away from anything that leaves the PCB.
- Add a ferrite bead on the 3.3V line between the power plane and the MCU's digital VDD pins — this prevents switching current from propagating onto the power distribution as a secondary antenna.
- Check for floating copper: any copper fill on signal layers not stitched to ground will pick up clock noise capacitively and re-radiate it.
The spread-spectrum option wasn't enabled — I didn't even know it existed in CubeMX. Just enabled it and the peak dropped from +6 dB over limit to +1 dB. Still failing but much closer. Going to try the ferrite bead on VDD next and add the crystal guard ring.
That 5 dB improvement from spread-spectrum alone is about typical. To get the last dB or two you'll likely need the guard ring and possibly a look at whether any cables attached to the board are resonant near 200 MHz — a 37 cm pigtail is a quarter-wave at 196 MHz. Common-mode ferrite clamps on I/O cables are the last-resort fix but they work well if cable emission is the dominant path.