How Do You Reduce EMI in PCB Design?

Detailed Explanation

EMI reduction in PCB design is primarily a layout discipline. Filtering and shielding can address residual problems, but the fundamental sources of electromagnetic interference — switching loops, return path discontinuities, fast signal edges, and unfiltered power supply noise — are most cost-effectively addressed in the circuit topology and PCB layout rather than after the fact.

This guide covers the EMI reduction techniques in priority order, starting with those that provide the greatest return for the effort invested. For background on what EMC is and how it affects product compliance, see the EMC topic hub. For the formal Australian certification process — NATA-accredited lab testing, Declaration of Conformity, and RCM marking — see how to get RCM certification in Australia. The applicable standard determines the specific emissions limits your design must meet — CISPR 32 for most commercial electronics, IEC 61000-6-4 for industrial equipment; see which Australian EMC standard applies to your product for the product-category decision.

1. Minimise Switching Loop Area

The switching loop in a power supply — the path traversed by the peak instantaneous current when the MOSFET turns on or off — behaves as a small loop antenna. Its radiation efficiency is proportional to its enclosed area. Halving the loop area reduces radiated emissions from that loop by approximately 6 dB (a 2× improvement in field strength at the measurement antenna).

For a buck or boost converter, the critical switching loop is defined by:

• The MOSFET drain (or source) connection
• The freewheeling diode (or synchronous FET)
• The input bypass capacitor

These three components form a loop. Layout them so the loop is as small as physically possible: the MOSFET, diode, and input capacitor should be adjacent, with short, wide traces connecting them, and the loop should sit directly over a solid ground plane.

The switch node copper (the node connecting MOSFET, diode, and inductor) must be a small, compact area — not a large pour. A large copper area at the switch node increases capacitance to nearby traces and planes, coupling the high dV/dt switching transient directly into adjacent circuitry. See how should you lay out a buck converter PCB? for the specific layout rules; they apply identically to boost and other switching topologies.

2. Maintain a Solid Ground Plane

Every signal current returns to its source via the path of least impedance. At high frequencies, that path is not "shortest electrical route around the board" — it is the path of least inductance, which is typically the return path directly beneath the signal trace in the ground plane. If the ground plane is interrupted by a slot, a via clearance, a routed trace, or a plane split, return currents must detour around the gap. This detour increases the effective loop area of the signal-return pair and creates a dipole antenna.

Rules for the ground plane:

• No traces routed through the ground plane layer under high-speed or switching circuits.
• No plane splits under active circuitry unless a genuine isolation requirement justifies it. Mixed analog-digital designs should use a single continuous ground plane with careful placement, not a split. See how do you design PCB power and ground plane layouts?.
• Stitch all ground layers together with via stitching at least every λ/10 at the highest frequency of concern (< 12 mm at 2.4 GHz; < 30 mm at 1 GHz; < 150 mm at 200 MHz). This prevents resonant cavities from forming between plane layers.
• All copper pours on signal layers should be connected to ground (stitched with vias) if they are intended as reference pours — floating copper pours act as capacitively-coupled antenna elements.

3. Decouple Power at Every Active Device

High-frequency current drawn by ICs during switching transitions must be supplied locally — if the IC has to draw that current from the bulk capacitor across the board, the trace inductance of the supply path causes a voltage transient at the IC's supply pin. This transient radiates.

Place at least one low-ESR ceramic capacitor (100 nF, X5R or X7R, 0402 footprint) directly at each VDD or AVDD pin with traces shorter than 1 mm to both the supply pin and the nearest via to the ground plane. A second smaller capacitor (10–100 pF) in parallel addresses GHz-range noise.

Practical rules:

• Capacitor placement comes before trace routing — connect the IC pins to the decoupling caps first, then route the supply rail to the caps from the power delivery network.
• For ICs with multiple power pins (a common pattern in FPGAs, SoCs, and radio ICs), each power pin needs its own dedicated decoupling capacitor. Do not share a single capacitor across multiple power pins.

For a full treatment of decoupling capacitor placement, see how should you place decoupling capacitors on a PCB?.

4. Manage Signal Edge Rates

The harmonic content of a digital signal extends to approximately the frequency where the rise time becomes the limiting factor: f_knee ≈ 0.35 ÷ t_rise. A signal with a 1 ns rise time has significant energy to 350 MHz; a 5 ns rise time is limited to 70 MHz.

For signals that do not need fast edges for timing reasons, adding a small series resistor (10–100Ω) in the signal trace slows the edge rate by forming an RC with the trace and load capacitance. This is particularly effective on:

• Clock outputs from MCUs driving long traces
• GPIO lines driving off-board loads
• SPI and I2C buses at shorter-than-maximum distances where slower edges are acceptable

The series resistor should be placed at the driver end of the trace (not the receiver), so the slow edge is present along the full trace length. The trace from the series resistor to the driver should be as short as possible. For how edge rates connect to transmission-line effects at the PCB level, see signal integrity in PCB design.

5. Control Impedance on Fast Signals

Uncontrolled impedance on high-speed traces causes signal reflections — the reflected waveform is additional high-frequency energy that contributes to radiated emissions. A trace that should be 50Ω but is routed at an arbitrary width can present 70–130Ω, creating a reflection coefficient of 0.17–0.44 — measurable both as signal degradation and as increased emissions.

Route fast clock signals, high-speed serial interfaces (USB, Ethernet, LVDS), and RF traces as controlled-impedance transmission lines matched to the driver and receiver impedance. See what is controlled impedance PCB design? for the calculation method.

6. Filter Interfaces and Cable Ports

Every connector on the PCB is a potential antenna. Filtering at connector interfaces attenuates high-frequency noise before it reaches the cable:

• Ferrite beads (on individual signal lines and power supply ports): effective above 30 MHz; select the impedance-frequency curve to match the noise frequency of concern. Murata BLM03AX series (0402) is a common choice for 100–500 MHz filtering at signal lines.
• Common-mode chokes (on differential pairs like USB, Ethernet, RS-485): attenuate common-mode noise without distorting the differential signal. Select a common-mode choke rated for the differential signal frequency and high impedance at the noise frequency.
• Pi filters (capacitor–ferrite–capacitor at power supply ports): provide a broader attenuation characteristic than a ferrite bead alone. A 100 nF capacitor on each side of a ferrite bead is the standard approach for USB and connector power pins.
• ESD protection diodes at every external interface pin serve dual purpose: they protect against electrostatic discharge (immunity) and their capacitance, combined with a series resistor or ferrite, forms a low-pass filter (emissions).
• Galvanic isolation: when a ground potential difference between connected boards or external equipment is the primary source of conducted noise — common in industrial systems where RS-485 cables run between equipment on different mains branches — an optocoupler or digital isolator on the interface lines breaks the ground loop entirely, eliminating the conducted path rather than filtering it. See Optocoupler vs Digital Isolator for selecting between the two technologies.

7. Shielding

Shielding — a conductive enclosure around a noise source or a sensitive circuit — reduces both radiated emissions and susceptibility to external fields. On a PCB, shielding is typically implemented as:

• Board-level metal shield cans: soldered to a continuous shield fence footprint on the PCB; enclose the switching power supply section or RF module. Shield cans must be connected to ground with a direct, low-impedance bond at multiple points around the perimeter.
• PCB copper ground pour on the same layer: a ground pour surrounding a high-frequency clock oscillator or switching node reduces near-field coupling to adjacent circuitry. Must be connected to the ground plane with stitching vias.

For Zeus Design's PCB layout team specialising in EMC-compliant circuit board designs — covering ground plane architecture, switching loop minimisation, and pre-compliance scan support — contact Zeus Design to discuss your board's EMC requirements.

Design Considerations

• Layer stackup determines your EMC options: a 2-layer board has limited EMC layout flexibility — signal and ground often share the same layers. A 4-layer board with dedicated ground and power planes provides the ground plane continuity needed for serious EMC performance. Design the layer stackup before placing a single component. See what is a PCB stack-up, and how do you design one?.
• Asymmetric return paths worsen EMC: if a high-frequency trace routes from one corner of the board to another across the top layer, but the return path in the ground plane is discontinuous along that route, the signal-return pair forms a large loop. Route signals so that the return path is always a direct, uninterrupted path beneath the signal trace.
• Chassis ground and PCB ground: in mains-powered products with a metal chassis, the PCB ground (signal reference) and the chassis ground (earth safety ground) have a different relationship at high frequency than at DC. At frequencies above a few MHz, the chassis becomes a large ground plane that dominates the common-mode impedance of the system. Bond the PCB ground to the chassis at one or more low-impedance points to control the common-mode current path.

Common Mistakes

• Adding filtering after layout is complete: ferrite beads and pi filters added as an afterthought are less effective than layout-based EMI reduction. If the switching loop is large and the ground plane has cuts, adding a ferrite bead on the supply line treats a symptom while the source remains. Fix the layout first.
• Floating copper pours: copper fills on signal layers that are not connected to ground or a supply net act as capacitively coupled parasitic elements. They pick up switching noise from nearby traces and re-radiate it. All copper fills should be either explicitly connected (to ground, via stitching) or removed.
• Via fences spaced too widely: ground stitching vias placed at greater than λ/10 spacing allow resonant modes to form between them, which can increase emissions at the resonant frequency rather than reducing them. Check stitching via spacing against the highest frequency of concern.
• Overlooking crystal oscillator emissions: MCU crystal oscillators are a consistent source of narrowband radiated emissions at the crystal frequency and its harmonics. Poor crystal circuit layout (traces too long, no local ground pour, no guard ring) exacerbates these emissions. Keep crystal traces short, use a local ground pour, and verify in pre-compliance testing.
• Misidentifying the emissions source in a failing product: a product that fails radiated emissions at 200 MHz may be failing because of a 200 MHz clock harmonic, a 200 MHz switching noise harmonic, cable antenna resonance at 200 MHz, or board resonance. Diagnosing the source (near-field scanning, probe isolation) before adding filtering prevents shotgun approaches that increase cost and add complexity without solving the problem.