What Is the Difference Between Combinational and Sequential Logic?

Detailed Explanation

The distinction between combinational and sequential logic is the most important structural distinction in digital design. Combinational circuits are pure functions — predictable and memoryless. Sequential circuits have memory, enabling them to implement behaviour that depends on history: counters, registers, state machines, and all finite-state control logic.

Combinational Logic: Outputs From Inputs Alone

A combinational circuit's output at any instant depends only on its inputs at that instant. The same set of inputs always produces the same output, regardless of what happened before.

Examples:

• A 2-input AND gate: output = A AND B, always.
• A 4-to-1 multiplexer: output = one of four inputs, selected by a 2-bit select signal.
• A binary adder: sum = A + B, carry = overflow of A + B.
• An address decoder: one of N outputs goes high based on the binary input address.

Combinational logic can be described by a truth table (for small inputs) or a Boolean expression. Propagation delay is the key timing parameter — the maximum time from any input change to the output settling at the correct value. This delay limits how fast the circuit can operate.

Sequential Logic: Adding Memory with Flip-Flops

Sequential logic adds state — memory that persists between clock cycles. This enables:

• Counting: remembering how many events have occurred.
• Storing: holding a value until needed.
• Sequencing: implementing step-by-step behaviour (state machines).
• Communication: serialising parallel data into bit streams.

The fundamental memory element is the D flip-flop:

     D ──────┐
             │    ┌──────────────┐
     CLK ────┼────┤ D         Q ├──── Q
             │    │             │
             └────┤ CLK      /Q ├──── /Q (inverted output)
                  └──────────────┘

Behaviour:

• On the rising edge of CLK (for a positive-edge-triggered flip-flop): Q captures the value of D at that exact moment.
• Between clock edges: Q holds its value — it does not change even if D changes.
• /Q is always the complement of Q.

This is the key property: the flip-flop is a 1-bit memory that is updated only at clock edges.

Timing Constraints: Setup and Hold Time

For a flip-flop to reliably capture D at the clock edge, D must be stable for a minimum time before and after the edge:

• Setup time (t_su): D must be stable (not transitioning) for at least t_su before the clock edge. If D is changing within the setup window, the flip-flop may capture an undefined intermediate value.
• Hold time (t_h): D must remain stable for at least t_h after the clock edge. If D changes too soon after the clock edge, the captured value may be corrupted.

          ___________
CLK: ___|           |___
         ↑
         Clock edge

     |← t_su →|       |← t_h →|
D:   ________XXXXXXXX__________
              ^
              D must not transition here (setup and hold window)

Timing violations (setup or hold violations) cause metastability: the flip-flop enters an indeterminate state where Q is neither a clean 0 nor a clean 1. This resolves probabilistically — but during the resolution window, the Q output can cause downstream logic to behave incorrectly.

In synchronous digital design, timing analysis tools (STA — Static Timing Analysis) verify that setup and hold times are met across all flip-flops in the circuit before the design is implemented. This is a standard step in FPGA and ASIC design flows.

Registers: Parallel Flip-Flops

A register is a group of flip-flops sharing the same clock, storing a multi-bit value:

/* In embedded C, a 32-bit hardware register behaves like 32 flip-flops:
   each bit holds its state between clock cycles, changed only on write */
volatile uint32_t *gpio_odr = (volatile uint32_t *)0x40020014;
*gpio_odr = 0x00000020;    /* writes all 32 flip-flops simultaneously on one bus write */

In an FPGA, synthesising reg [31:0] data; in Verilog infers 32 flip-flops. The synthesis tool automatically maps these to the FPGA's flip-flop resources.

Counters and Shift Registers

Binary counter: a chain of flip-flops where each flip-flop's Q drives the clock of the next (ripple counter), or where all flip-flops share a clock and a combinational carry chain updates them (synchronous counter). A synchronous counter is preferred for timing analysis — all flip-flops update at the same clock edge.

Shift register: flip-flops connected in a chain where Q of one drives D of the next. Each clock edge shifts data one position through the chain. Used in serial communication protocols (SPI shifts data in and out 1 bit per clock) and in delay lines (8 flip-flops in a chain = 8-cycle delay).

Clock Domain Crossings

When two parts of a digital system operate with independent clocks — different frequencies or the same frequency but with no guaranteed phase relationship — a signal transferred between them requires special handling.

If a signal driven by Clock A is sampled by Clock B without synchronisation, Clock B's flip-flop may violate its setup or hold time whenever the signal transitions near a Clock B edge. This causes metastability.

Solution: dual-flop synchroniser (for single-bit signals):

Signal from         ┌────┐    ┌────┐
clock domain A: ────┤ FF ├────┤ FF ├────→ Synchronised to clock B
                    └────┘    └────┘
                     CLK_B    CLK_B

Two flip-flops clocked by Clock B in series. If the first flip-flop goes metastable, it has one full Clock B period to resolve before the second flip-flop samples it. With typical flip-flop MTBF (mean time between failures) at a given frequency, two flip-flops provide sufficient margin for most designs. Critical applications use three flip-flops or purpose-built synchroniser cells with characterised MTBF.

For multi-bit data: never use the dual-flop synchroniser directly on a multi-bit bus — each bit could resolve to different values, producing a corrupted composite word. Use an asynchronous FIFO (with Gray-coded pointers that change only 1 bit per count, making them safe to synchronise independently) or a handshake protocol.

Synchronous vs Asynchronous Designs

Synchronous design (used in nearly all modern digital systems): all flip-flops share a common clock (or a small set of related clocks). All state transitions occur at clock edges. Timing analysis is tractable: STA tools can verify all setup/hold times statically.

Asynchronous design: state transitions are triggered by signal changes rather than a global clock. Avoids clock distribution and can be faster in theory, but timing analysis is much more difficult. Used in specific low-power or high-performance circuits but rarely in mainstream embedded or FPGA design.

For more on how sequential logic is used to implement control behaviour, see how to design a finite state machine.

For FPGA-based sequential designs with complex clock domain structures, Zeus Design's hardware team designs and implements digital systems from specification through to FPGA prototyping.

Design Considerations

• Always close combinational paths with flip-flops at clock boundaries. In an FPGA or ASIC, the longest combinational path between two flip-flops determines the maximum clock frequency. Keep logic depth (gate stages per path) low. Pipelining — adding intermediate flip-flops in long paths — increases latency but allows a higher clock frequency.
• Avoid inferred latches in HDL. In Verilog or VHDL, an if/case statement in a combinational block (always @(*) in Verilog) that does not cover all cases infers a latch — the synthesis tool infers that the signal must hold its value for the uncovered cases. Always include an else branch or a default case. Enable latch inference warnings in the synthesis tool.
• Use the dual-flop synchroniser for every clock domain crossing. Do not rely on signal timing being "fast enough" to not cause problems at a CDC. Even a signal that appears reliable in simulation or at nominal conditions can fail at temperature extremes or process variation.

Common Mistakes

• Treating asynchronous resets as synchronous. An asynchronous reset on a flip-flop takes effect immediately on the reset signal edge, not at the next clock edge. If the reset is released asynchronously near a clock edge, the flip-flop may not capture its initial value correctly. Use synchronous reset release (a "reset synchroniser" that delays the deassertion of reset by one or two clock cycles) when transitioning out of reset in a clocked system.
• Connecting a combinational path directly between two clock domains. If signal A is driven by Clock A logic and signal B = NOT(A) is placed in Clock B's fanout, the inversion delay is so small that B changes almost simultaneously with A — still asynchronous to Clock B, and still requires a synchroniser.
• Using a shared variable for inter-task communication without atomic access. In embedded firmware, a shared 32-bit variable accessed from both a task and an ISR is the software equivalent of a clock domain crossing. On a Cortex-M, a 32-bit aligned read or write is atomic, but read-modify-write sequences (x |= bit) are not. Use atomic operations (__atomic_fetch_or) or disable interrupts around read-modify-write if the variable is shared.
• Ignoring hold time violations in favour of setup time. Setup time violations are fixed by reducing the clock frequency or shortening the logic path. Hold time violations cannot be fixed by slowing the clock — they require adding delay to the data path (extra gates, buffer cells). In FPGAs, hold time violations appear when hold analysis shows negative slack; they require the tools to insert delay buffers, which happens automatically during implementation but can be missed if timing closure is not verified.