What Are Logic Gates and How Do They Work?

Detailed Explanation

Every digital system — microcontrollers, FPGAs, CPUs, memory arrays — is ultimately built from combinations of a handful of fundamental building blocks: logic gates. Each gate implements one Boolean function, and by chaining gates together any digital behaviour can be expressed.

The Six Fundamental Gates

AND gate

Output is 1 (high) only when all inputs are 1. In Boolean algebra: Y = A · B (the dot denotes AND; often written just AB).

OR gate

Output is 1 when any input is 1. Boolean: Y = A + B (the plus denotes OR).

NOT gate (inverter)

Single-input gate; output is always the complement of the input. Boolean: Y = Ā (A with a bar).

NAND gate (NOT-AND)

Output is 0 only when all inputs are 1 — the complement of AND. Boolean: Y = AB̄. NAND is a universal gate: any logic function can be built from NAND gates alone.

NOR gate (NOT-OR)

Output is 1 only when all inputs are 0 — the complement of OR. Boolean: Y = A + B̄. NOR is also a universal gate.

XOR gate (exclusive OR)

Output is 1 when inputs differ — when exactly one input is 1. Boolean: Y = A ⊕ B. XOR is widely used for parity generation/checking, binary addition (half-adder), and comparison circuits.

The complement of XOR is XNOR (exclusive NOR): output is 1 when inputs are equal: Y = A ⊙ B. XNOR is used in equality comparators and LFSR (linear feedback shift register) implementations.

CMOS Implementation

In modern digital circuits, logic gates are implemented in CMOS (Complementary Metal-Oxide-Semiconductor) technology. Every CMOS gate uses two complementary transistor networks:

• Pull-up network (PMOS transistors): connects the output to the supply voltage (VDD) when the output should be logic high.
• Pull-down network (NMOS transistors): connects the output to ground (GND) when the output should be logic low.

A NAND gate (the most natural CMOS primitive):

• Pull-up: two PMOS transistors in parallel — if A=0 OR B=0, the output is pulled to VDD.
• Pull-down: two NMOS transistors in series — only if A=1 AND B=1, the output is pulled to GND.

An AND gate requires a NAND followed by an inverter — an extra transistor stage that adds propagation delay. This is why NAND is preferred in practice: it is both the natural CMOS implementation and a universal gate.

Similarly, NOR is the natural CMOS implementation of the OR function:

• Pull-up: two PMOS in series.
• Pull-down: two NMOS in parallel.

OR requires NOR + inverter.

Boolean Algebra: Simplifying Logic

Boolean algebra provides rules for simplifying logic expressions before implementing them in gates. Key laws:

De Morgan's theorems are particularly important: they explain how NAND gates can replace AND + NOT, and how NOR gates can replace OR + NOT. They also appear whenever active-low signals are used in hardware design.

Example simplification: Suppose a circuit needs Y = AB + AC. Factoring: Y = A(B + C) — reduces from three gates (two ANDs, one OR) to two (one AND, one OR).

Universal Gates: NAND-Only Logic

Any logic function can be expressed using only NAND gates. This matters because it means a chip manufacturer can build one type of gate cell and implement any digital function from it.

• NOT from NAND: connect both inputs of a 2-input NAND to the same signal → NOT
• AND from NAND: NAND followed by NOT (= NAND followed by NAND-as-NOT)
• OR from NAND: by De Morgan's, OR(A,B) = NAND(NOT(A), NOT(B))

Similarly, NOR is also universal — any function can be built from NOR gates alone. XOR is not universal by itself.

In real FPGA design, LUTs (Look-Up Tables) generalise the concept of universal gates: a 4-input LUT can implement any 4-input Boolean function, making it effectively a configurable universal logic element. See what is an FPGA for how LUTs work.

Logic Families and Voltage Levels

Gates are manufactured in various logic families with different voltage levels and drive strengths:

• 5 V CMOS (4000 series): classic CMOS, slow but wide supply range.
• 5 V TTL (7400 series): bipolar transistor logic, different switching thresholds than CMOS.
• 3.3 V LVCMOS: modern MCU and FPGA I/O standard.
• 1.8 V / 1.2 V CMOS: found in modern SoCs and DDR interfaces.

When connecting devices from different logic families, check that the output's logic high voltage (V_OH) exceeds the receiver's minimum high threshold (V_IH), and that the receiver's absolute maximum input voltage is not exceeded by the driver. See the digital topic hub for more on logic family compatibility.

Design Considerations

• Fan-out matters. Each gate output can drive only a limited number of gate inputs (limited by its drive current). Exceeding the specified fan-out causes the output voltage to not fully reach the logic thresholds. Add a buffer gate if driving many loads.
• Propagation delay accumulates. A chain of N gates has a propagation delay of N × t_pd (approximately). The maximum clock frequency in a synchronous circuit is limited by the longest combinational path through gates between flip-flops. Minimise this critical path by reducing gate count or using faster logic families.
• Glitches in combinational logic. When multiple inputs change simultaneously, intermediate states cause momentary incorrect outputs (hazards or glitches). These are usually harmless in combinational-only circuits but can cause false register captures in sequential circuits. Use synchronous design practices to avoid glitch-sensitive behaviour.

Common Mistakes

• Leaving unused gate inputs floating. An unconnected CMOS input floats at an indeterminate voltage, drawing excessive current and producing unpredictable outputs. Tie unused AND gate inputs to VDD (1), OR gate inputs to GND (0), or use a standard logic IC with only the inputs needed.
• Mixing logic family voltage levels without level translation. Connecting a 5 V output to a 3.3 V input can exceed the absolute maximum input voltage rating and damage the receiving device. Always check both V_OH of the driver and V_IH_max of the receiver before direct connection.
• Implementing XOR with NAND/NOR without timing analysis. The NAND-based XOR implementation uses a feedback path with different propagation delays; the output can glitch. For timing-critical paths, use a dedicated XOR gate or confirm the synthesis tool handles hazard elimination.
• Treating NAND/NOR as equivalent to AND/OR in timing estimates. NAND and NOR gates are faster than AND and OR in CMOS — AND/OR require an extra inverter. Timing estimates based on AND/OR gate counts underestimate the actual critical path if the implementation uses AND/OR. Use synthesis tool timing reports, not manual gate counts, for timing analysis.