Digital

Digital circuit design deals with signals in discrete binary states — logic high and logic low — and the systems built from them. Modern digital systems range from simple combinational logic gates to complex FPGAs, CPUs, and SoCs. Understanding timing, logic families, bus signalling, and the boundary between digital and analog is fundamental to building reliable hardware.

What Is Digital Circuit Design?

Digital design covers:

• Combinational logic — circuits whose outputs depend only on current inputs: AND, OR, NOT, XOR gates, multiplexers, encoders, decoders.
• Sequential logic — circuits with state that depends on previous inputs: flip-flops, registers, counters, and finite state machines.
• Bus and interface design — the electrical and timing requirements of digital buses: LVTTL, LVCMOS, LVDS, and high-speed differential signalling.
• Timing analysis — ensuring setup and hold times are met, clock skew is managed, and metastability is handled at asynchronous domain crossings.
• Digital-to-analog interface — GPIO configuration, PWM generation, and the role of the ADC/DAC interface layer.

Why Digital Design Matters

Digital systems are not immune to analog effects. At high speeds and in dense PCBs:

• Signal integrity degrades at fast edge rates — reflections, crosstalk, and transmission-line effects appear in signals that would be clean at lower speeds.
• Timing margins close as frequencies rise — a system that appears to work correctly at 80 MHz may fail intermittently at 100 MHz due to setup-time violations.
• Power integrity becomes critical — fast digital switching draws large transient currents that must be supplied by nearby decoupling capacitors, or supply voltage droops and logic errors follow.
• EMC — digital logic is typically the dominant source of radiated emissions in mixed-signal products. Clock harmonics and fast GPIO edge rates generate broadband noise.

Key Concepts

• Logic family — a family of digital ICs sharing compatible voltage levels and drive strengths (TTL, CMOS, LVTTL, LVCMOS, LVDS, HSTL). Voltage compatibility between families must be verified when interfacing devices.
• Setup time and hold time — the minimum time a data signal must be stable before and after a clock edge for a flip-flop to reliably capture it. Violations cause metastability.
• Propagation delay — the time between an input change and the resulting output change. Critical for timing analysis in combinational and sequential circuits.
• Clock domain crossing (CDC) — transferring a signal between two circuits with independent clocks. Without proper synchronisation (dual flip-flop, handshake, FIFO), metastability can cause system failures.
• Fan-out — the number of inputs a single logic output can drive within its specified drive current and voltage swing limits.
• PWM (Pulse-Width Modulation) — a digital technique for generating an effective analog output by varying the duty cycle of a fixed-frequency digital signal, commonly used for motor speed control, LED dimming, and DAC-less audio.

Common Tools and Software

• EDA tools — most PCB EDA tools (KiCad, Altium) include signal integrity simulation and timing analysis tools suitable for digital PCB design.
• Logic analysers — Saleae Logic (USB, excellent multi-channel protocol decode), Rigol LA5000 series (benchtop). Essential for debugging digital buses, capturing protocol traffic, and verifying timing.
• Oscilloscopes — needed alongside a logic analyser for measuring signal quality: edge rates, ringing, overshoot, and voltage levels at the 0/1 decision threshold.
• FPGA and HDL tools — for programmable logic: Vivado (Xilinx/AMD, includes a simulator), Quartus Prime (Intel, free version available), ModelSim/Questa (industry standard HDL simulator), Gowin EDA (for Gowin FPGAs). For most embedded electronics work, FPGA tools are not required.

Common Mistakes

• Treating digital signals as ideal at high speeds — at fast edge rates (sub-nanosecond), PCB traces longer than a few centimetres behave as transmission lines. Reflections appear as ringing on the oscilloscope and can cause false triggers at the receiver. Match trace impedance to the driver/receiver impedance or add series termination resistors.
• Inadequate decoupling for fast digital ICs — a CMOS output switching from low to high draws a large transient current from the supply to charge line capacitance. Without low-ESR decoupling capacitors placed close to the IC's supply pin, the supply voltage droops during switching and can cause logic errors.
• Mismatching logic family voltage levels at interfaces — interfacing a 3.3 V output to a 5 V-only input (or vice versa) without a level shifter causes unreliable logic levels or permanent damage. Check V_OH, V_IH, and the absolute maximum input voltage in both devices' datasheets before connecting directly.
• Ignoring clock domain crossings — signals that cross between clock domains without a synchroniser cause metastability. Metastability failures are intermittent and often appear only at temperature extremes or on specific production units, making them extremely difficult to debug after release.
• Overlooking digital logic as an EMC emissions source — digital logic clocks and fast GPIO edges are typically the dominant source of radiated emissions in mixed-signal products. Clock frequencies and their harmonics, fast bus signals, and oscillator lines without series termination all contribute. EMC must be considered during digital PCB layout, not as an afterthought.

Common Questions

What is the difference between TTL and CMOS logic levels?

TTL (Transistor-Transistor Logic) uses a supply voltage of 5 V, with a logic high output typically above 2.4 V and a logic low below 0.4 V. CMOS logic levels scale with the supply voltage and are more symmetric: a 3.3 V CMOS output drives high above about 2.4 V and low below about 0.4 V, but the input thresholds are typically 70% and 30% of the supply. When interfacing devices from different voltage families, check the datasheet voltage threshold and maximum input voltage specifications — mismatched logic levels are a common source of intermittent communication failures.

Why does my digital signal look "noisy" on the oscilloscope?

Fast digital signals driven by CMOS output drivers have fast edge rates (sub-nanosecond rise times in some cases) that cause reflections on any trace long enough to act as a transmission line. A PCB trace longer than about λ/6 at the signal's knee frequency — which for a 1 ns rise time is only a few centimetres — should be treated as a transmission line and terminated. Ground bounce, crosstalk, and power supply noise also appear as noise on digital signals, particularly if decoupling is inadequate.

How do I safely cross a clock domain boundary?

Use a double-register synchroniser (two flip-flops clocked in the destination domain in series) for single-bit control signals. For multi-bit data, use a properly designed asynchronous FIFO or a handshake protocol that ensures the entire word is stable before being sampled in the destination domain. Never assume a signal crossing clock domains is safe without explicit synchronisation. Zeus Design designs digital hardware and firmware for embedded and FPGA-based systems.

Knowledge Base

Digital Foundations

• What Are Logic Gates and How Do They Work? — AND, OR, NOT, NAND, NOR, XOR: truth tables, CMOS implementation, Boolean algebra, and universal gates
• Binary and Hexadecimal: Number Systems in Embedded Electronics — counting in binary and hex, two's complement signed integers, and bitwise operations in C
• What Is the Difference Between Combinational and Sequential Logic? — D flip-flops, setup and hold time, registers, metastability, and clock domain crossing synchronisers
• How Do You Design a Finite State Machine? — Moore vs Mealy machines, state diagrams, one-hot vs binary encoding, C switch statement FSM, and Verilog implementation

FPGA and Programmable Logic

• What Is an FPGA and How Does It Work? — LUTs, BRAM, DSP blocks, Verilog vs VHDL, the FPGA design flow, and major vendor families
• FPGA vs Microcontroller vs ASIC: Which Should You Use? — decision framework: when to choose each platform, volume economics, ASIC NRE costs, hybrid FPGA+MCU and Zynq SoC approaches
• How Do You Write Verilog and VHDL for an FPGA? — modules, always blocks, blocking vs non-blocking assignments, latch inference rules, and test bench simulation basics
• FPGA Development Flow: From HDL to Working Hardware — synthesis, place-and-route, XDC timing constraints, reading WNS/TNS timing reports, timing closure strategies, bitstream generation, and JTAG vs SPI flash programming in Vivado and Quartus

GPIO and Microcontroller Digital Interfaces

• How Do GPIO Pins Work? — input/output configuration, push-pull vs open-drain, pull-ups, interrupt-capable pins
• PWM Explained: Frequency, Duty Cycle, Dead-Time, and Hardware Timers — duty cycle formula, frequency selection, resolution vs frequency trade-off, dead-time for H-bridge drives, hardware timer vs software PWM, common applications

Signal Integrity and High-Speed Design

• Signal Integrity in PCB Design: Reflections, Crosstalk, and Termination — when traces become transmission lines; reflection coefficient; source vs end termination; crosstalk and the 3W rule; reference plane continuity; edge rates and bandwidth

Digital Communication Protocols

The Communications topic covers the most widely used digital protocols in embedded systems: SPI, I2C, UART, and their comparison.

Digital Debugging Tools

• Logic Analyser vs Oscilloscope: Which Should You Use? — choosing between digital and analog debug instruments for different problem types

Microcontroller Digital Design

See the Embedded Systems topic for microcontroller-level digital design, including interrupt configuration, PWM timer setup, and peripheral interfacing.