What Is a Voltage Divider and How Does It Work?

Detailed Explanation

The voltage divider is the most fundamental analog circuit in electronics: two resistors, three connections, and a single equation. Every ADC input level-shift, every battery measurement circuit, every resistive sensor bridge, and many op-amp bias networks are applications of the voltage divider. Its simplicity is valuable but can be misleading — the loading effect catches engineers who apply the formula without considering what connects to the output.

The Voltage Divider Formula

Connect R1 from Vin to an intermediate node, and R2 from that node to GND. The output voltage at the intermediate node is:

Vout = Vin × R2 / (R1 + R2)

This follows directly from Ohm's Law. The total voltage Vin appears across the series combination of R1 and R2. The voltage across R2 is the same fraction of Vin as R2 is of the total resistance.

Example: 5V to 3.3V level shift To reduce a 5V logic signal to 3.3V for an ADC:

Vout/Vin = 3.3/5.0 = 0.66
R2/(R1+R2) = 0.66

A common solution: R1 = 18 kΩ, R2 = 33 kΩ → Vout = 5 × 33/(18+33) = 3.24V ≈ 3.3V.

Example: Battery voltage monitoring To measure a 12V battery with a 3.3V ADC (max input = 3.3V), scale 12V → 3.3V:

Vout/Vin = 3.3/12.0 = 0.275

R1 = 100 kΩ, R2 = 33 kΩ → Vout = 12 × 33/133 = 2.98V → ADC reads full battery as 2.98V (within range). Adjust for exact ratio as needed.

The Loading Effect

The formula above assumes the output is connected to a load with infinite impedance (draws zero current). In practice, any real load has finite impedance, and current flows through it, reducing the voltage at the output node.

When a load resistance R_L is connected to Vout:

Effective R2 = R2 ∥ R_L = (R2 × R_L) / (R2 + R_L)
Vout_loaded = Vin × (R2∥R_L) / (R1 + R2∥R_L)

Example: R1 = 10 kΩ, R2 = 10 kΩ, Vin = 5V → unloaded Vout = 2.5V. Connect a 10 kΩ load: R2∥R_L = 5 kΩ → Vout = 5 × 5/(10+5) = 1.67V. That is a 33% voltage error — far larger than most applications can tolerate.

The rule of thumb: the load impedance should be at least 10× the Thevenin output resistance (Rth = R1∥R2) to keep the loading error under approximately 10%.

Thevenin Equivalent

The Thevenin equivalent of a voltage divider is the model that explains why loading affects the output. Replace the voltage divider with:

• Thevenin voltage (Vth): The open-circuit output voltage = Vin × R2/(R1+R2).
• Thevenin resistance (Rth): The resistance seen looking back into the output node with the voltage source replaced by a short: Rth = R1 ∥ R2.

This is the "source impedance" of the divider. Any connected load interacts with this impedance. A low-impedance load — even one that draws modest current — causes a significant voltage drop across Rth.

To drive a low-impedance load without loading error, add a unity-gain op-amp buffer (voltage follower) between the divider output and the load. The follower's high input impedance doesn't load the divider, and its low output impedance drives the load without error.

Applications

ADC input scaling: Voltage dividers are commonly used to scale sensor voltages or higher-voltage rails to within the ADC's input range. The ADC input impedance is typically very high (MΩ for a CMOS ADC during sampling), so loading is minimal. However, if the ADC has a sample-and-hold capacitor on its input, there will be a brief charge injection current during sampling. Keep Rth low enough that the capacitor can charge fully within the sampling time. A rule of thumb for SAR ADCs: Rth should be under 1 kΩ for sampling times under 1 µs.

Bias networks for op-amps: On a single-supply circuit, a voltage divider sets the mid-supply bias voltage (Vcc/2) applied to the non-inverting input of an op-amp. Because the op-amp's input draws negligible current, loading is minimal. However, the Thevenin resistance of the divider appears in series with the op-amp's input and sets the source impedance seen by the input bias current cancellation resistor.

Resistive sensor measurement (thermistor, NTC, potentiometer): A thermistor or other variable resistor in one leg of a voltage divider converts resistance to voltage. With a fixed reference resistor in R1 and the thermistor as R2, the output voltage changes as temperature changes. The same formula applies, with R2 being the temperature-dependent resistance.

For circuit design that integrates analog measurements, level-shifting, and ADC front ends into an embedded product, Zeus Design's engineering team handles the full design cycle — contact Zeus Design.

Design Considerations

• Set the quiescent current based on power and loading requirements. Higher quiescent current (lower total resistance) reduces loading error but wastes power. For a battery-operated product measuring a high-impedance ADC input, total resistance of 100 kΩ–1 MΩ is reasonable; the ADC's high input impedance prevents significant loading. For biasing an op-amp non-inverting input, 10 kΩ–100 kΩ is typical.
• Use 1% resistors for accuracy-critical dividers. The ratio tolerance of a 5% resistor pair can produce a 10% error in Vout. For a battery measurement circuit where 5% voltage error translates to significant state-of-charge inaccuracy, use 1% E96 series resistors.
• Add a small capacitor across R2 for noise filtering. A 100 nF ceramic capacitor in parallel with R2 forms a low-pass filter with cutoff f = 1/(2π × Rth × C). For a 10 kΩ Thevenin resistance and 100 nF, the cutoff is about 160 Hz — filtering ADC input noise at higher frequencies.
• Account for resistor temperature coefficient in precision applications. Standard thick-film resistors have a temperature coefficient of ±100–200 ppm/°C. In a ratio network, matching resistors from the same manufacturer and lot minimises ratio drift with temperature. For high-precision voltage references, use thin-film resistors with ±10–25 ppm/°C.

Common Mistakes

• Using a voltage divider as a voltage regulator. A divider's output voltage is set by the load impedance as well as the resistor ratio. Any change in load current changes the output voltage. Use a proper linear regulator or DC-DC converter for regulated power.
• Ignoring the loading effect. Calculating Vout with the unloaded formula and then connecting a low-impedance load produces a lower output than expected. Always calculate the loaded output voltage or verify that the load impedance is at least 10× Rth.
• Driving the ADC's sample-and-hold capacitor through a high-impedance divider. If Rth is too high, the ADC's input capacitor cannot charge to the input voltage within the sampling window, causing a systematic measurement error. Check the ADC datasheet for maximum recommended source impedance; if your divider Rth exceeds it, buffer the divider output with an op-amp follower.
• Placing the divider output capacitor on the wrong node. A capacitor should go across R2 (between the output node and GND) to filter noise on the measured voltage. A capacitor placed above R1 (between Vin and the output node) is in the wrong position and will not filter as intended.