What Is I2S (Inter-IC Sound)?

Detailed Explanation

I2S was developed by Philips (now NXP) in 1986 specifically to connect digital audio ICs — DACs, ADCs, audio codecs, DSPs, and microcontrollers — without the overhead of a full-featured bus protocol. It carries nothing but linear PCM audio samples, making it simple to implement in hardware and straightforward to debug.

The three I2S signals

BCLK (Bit Clock) — clocks each bit of the audio sample onto or off the SD line. BCLK runs continuously at a frequency equal to the sample rate multiplied by the total number of bits transmitted per sample frame. For 48 kHz stereo at 24 bits per channel, BCLK runs at 2.304 MHz.

LRCK (Left-Right Clock, also called WS — Word Select) — transitions at exactly the sample rate (e.g. 48 kHz), with a 50% duty cycle. When LRCK is low, the left-channel sample is being transmitted; when high, the right-channel sample. The LRCK period defines one complete stereo frame.

SD (Serial Data) — carries audio samples MSB-first, transmitted synchronously with BCLK. In standard I2S format, the first bit of a sample appears on the SD line one BCLK cycle after the LRCK transition — this one-cycle delay is a deliberate part of the I2S specification and distinguishes it from left-justified or right-justified variants.

Master and slave roles

One device in an I2S system must be the master — it generates BCLK and LRCK. All other devices are slaves that lock to these clocks. On many microcontrollers, the I2S peripheral can be configured as either master (generating clocks) or slave (receiving clocks from an external codec or DSP). The master is typically the device that drives the system audio clocks, often a dedicated audio clock generator or the MCU itself when a precise audio clock is not required.

Variants: left-justified, right-justified, PCM

The Philips I2S specification uses a one-cycle offset between LRCK and the first data bit. Other variants omit this offset:

• Left-justified: data MSB appears on the same BCLK rising edge as the LRCK transition (no delay). Common in some codecs and DSPs.
• Right-justified: data is LSB-aligned within the frame, padding with zeros from the MSB side. Used by some older DACs.
• PCM/DSP mode: a single short sync pulse (one BCLK wide) replaces LRCK; used for TDM multi-channel audio.

Hardware I2S peripherals on most microcontrollers (STM32, ESP32, nRF52) support selection among these formats. Codec datasheets specify which formats they accept.

Practical Examples

A typical embedded audio player connects an STM32 microcontroller to an external audio DAC (such as the PCM5102A or MAX98357A) over I2S. The MCU reads compressed audio from flash, decodes it to PCM in software, and streams the decoded samples to the DAC over I2S using DMA. The DAC converts the digital PCM to an analogue audio waveform and drives a speaker directly. The MCU I2S peripheral acts as master, generating the BCLK and LRCK clocks; the DAC locks to them as a slave.

For audio capture, a MEMS microphone with a PDM interface (such as the MP34DT01) connects to a PDM-to-PCM decimation filter on the MCU, which outputs PCM over I2S to an audio codec or streaming engine. The nRF52840 and STM32H7 both include PDM/I2S peripherals suitable for microphone array capture.

Design Considerations

• Audio clock accuracy: I2S sample rates are usually exact multiples of 44.1 kHz or 48 kHz, and these two clock families are mathematically incompatible — you cannot derive both from a single integer-ratio PLL unless you use a fractional PLL or a dedicated audio clock IC. Products supporting both standard families (44.1 and 48 kHz) typically use a dedicated audio oscillator or a fractional-N synthesiser.
• I2C for codec configuration: the I2S bus carries only audio data — no control. Most audio codecs use a separate I2C bus for register configuration (volume, sample rate, format, input selection). Plan for both buses in hardware.
• DMA requirement: streaming audio at 48 kHz / 16-bit stereo = 1.536 Mbit/s means the MCU must feed the I2S peripheral a constant stream of data. Use DMA with a double-buffer (ping-pong) arrangement — the CPU fills one buffer while the DMA transmits the other. Polling-based I2S transfer causes audio glitches under any interrupt latency.
• PCB layout: keep I2S traces short and direct, with a continuous ground reference plane beneath the traces. For clocks above a few MHz, treat BCLK as a moderately high-speed signal and avoid long stubs. I2S is not a differential bus, so it is more susceptible to common-mode noise than CAN or RS-485.

Common Mistakes

• Mismatched format between MCU and codec: standard I2S, left-justified, and right-justified all look similar on a scope (three lines, similar frequencies) but produce corrupted audio if the MCU and codec are configured differently. Confirm the format from both datasheets before assuming they are compatible.
• Incorrect bit depth vs BCLK frequency: if the BCLK frequency does not match the sample rate × bit depth × 2 channels, the LRCK will not divide the BCLK into equal halves per sample period, and the audio will be corrupted or the codec will lose synchronisation.
• Forgetting the MCLK requirement: many audio codecs require a master clock (MCLK) input, typically 256× or 384× the sample rate, in addition to BCLK and LRCK. This must come from the MCU or an external oscillator — check the codec datasheet for the required MCLK-to-sample-rate ratio.
• Not using DMA: blocking on the I2S peripheral in a polling loop causes audio dropouts the moment any other interrupt fires. DMA is not optional for reliable audio streaming.