Electronics Design AUGot boards back from my first CM assembly run — tombstoning on 0402s and QFN bridging
Asked by stale_biscuit_03 ·
Finally bit the bullet and sent my first board to a CM for assembly rather than hand-soldering everything. Got the boards back yesterday and mostly they look okay but there are two issues I can't figure out:
Problem 1: Tombstoning on some 0402 passives
About 4 out of roughly 55 0402 caps and resistors have one end lifted off the pad. They're scattered around the board — not all in one area. I thought tombstoning was a pick-and-place problem but the CM says their machine is calibrated fine.
Problem 2: Solder bridging on one corner of a QFN-24
Two or three pads are shorted on one corner of the IC. The rest of the chip looks clean under a loupe. I drew the footprint myself from the datasheet land pattern, though I'm not 100% sure I handled the thermal pad paste layer correctly.
My question is: are these my design/footprint mistakes, or is this a CM process issue? I don't want to blame them for something I got wrong, but I also don't want to respin if the fix is on their end. This is my first time sending anything to a CM so I genuinely don't know who owns what.
3 Replies
Good news: these two defects have different root causes, and once you understand what's driving each one you'll know exactly where to push.
Tombstoning on 0402s
Tombstoning happens when one pad wets with solder before the other, and surface tension on the wetted side pulls the component upright. The scattered distribution you're describing — not clustered in one corner — usually rules out a board-level oven profile issue. That would show a zone pattern. Random scatter like yours almost always points to thermal asymmetry at the individual pad level.
Check each tombstoned part specifically for:
- One pad connecting to a ground pour or wide copper fill, the other going to a thin signal trace. The pour side sinks heat; the signal side reaches liquidus faster and wets first.
- A via very close to one pad (within ~0.5 mm). Vias pull heat away from the pad they touch, creating the same asymmetry.
- Different pad geometries on the two ends — if one is slightly larger, it holds more paste and that imbalance can be enough at 0402.
The fix for the next spin is to balance thermal mass on both pads. If one pad has to connect to a ground pour, add a short stub trace to the other pad so they have similar copper area and heat-sinking. The component placement best practices article covers this under the thermal symmetry section — worth re-reading with your layout open.
(Standard 0402 land pattern per IPC-SM-782A: 1.4 mm × 0.7 mm pads, 1.3 mm heel-to-heel — check your actual footprint against that and also confirm against your specific CM's DFM guide, as preferred dimensions vary.)
QFN-24 bridging on one corner
Bridging localised to one corner of a QFN is almost always either paste over-deposit on the thermal pad, or the component sitting slightly off-centre during placement so paste smears toward that corner.
The thermal pad is usually the culprit. If you put a single full-size aperture on the paste layer for the QFN exposed pad (or let KiCad default to 100% coverage), the paste deposit is too thick. During reflow, that big solder mass has nowhere to go except sideways — and it flows toward the signal pads at the corner. Standard practice is to split the thermal pad aperture into a grid pattern targeting around 50–60% paste coverage. Most footprint editors have a paste margin setting; in KiCad you can set individual aperture rectangles on F.Paste for that pad.
Ask the CM for their stencil file or aperture report for your build. If they used one big aperture for the thermal pad because none was defined in your Gerbers, that's a shared responsibility — but it's easy to fix on your side for the next spin.
Background on what the CM is doing at each step (and how paste printing feeds into the reflow stage): How does SMT PCB assembly work?
This is all very normal for a first CM build. You're not looking at a fundamentally broken design — you're calibrating between your design intent and their process. These are fixable.
On the QFN thermal pad paste specifically — there's an IPC guideline that's useful to know: IPC-7525 specifies a minimum aperture area ratio of 0.66 (aperture opening area divided by the area of the stencil wall). For a large square thermal pad with a standard 0.12 mm stencil, a single full-size aperture blows past the ideal paste volume.
The usual approach is to tile the thermal pad with a grid of smaller square or rectangular openings separated by ~1.5–2 mm bridges of stencil material. Target about 50–60% of the thermal pad area as aperture opening. That gives enough solder for a good thermal and mechanical joint without generating excess paste that migrates to the signal pads.
In KiCad, the cleanest way to do it is to define multiple paste aperture polygons directly on the F.Paste layer in the footprint editor, with gaps between them. Some designers use the Paste Margin field to reduce the single aperture, but a grid is more reliable at fine pitches.
One other thing to check: what stencil thickness did the CM use? 0.12 mm (120 µm) is common for mixed-component boards. For 0.5 mm pitch QFN, that's manageable, but some CMs step down to 0.10 mm locally for fine-pitch areas. Ask them what they ran and compare against the solder paste manufacturer's deposit volume spec for that pitch.
The area ratio calculation, stencil thickness guidelines by pitch, and thermal pad aperture segmentation are all covered in the solder paste and stencil design guide — worth reading before tweaking the paste layer on the next spin.
Good advice above. Before the next spin, request the following from the CM:
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AOI report — the automated optical inspection output for your build. It should show which components flagged and at which stage. If the QFN bridge was visible post-paste-print before reflow, that points at paste volume or placement. If it only appeared post-reflow, it's a thermal migration issue. For a breakdown of what AOI does and doesn't catch (and when X-ray and flying probe become relevant), see how PCB assemblies are tested and inspected.
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Stencil aperture file — either the stencil Gerber or their aperture report. This confirms what paste coverage they actually applied to the QFN thermal pad.
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Reflow profile — oven zone setpoints and, ideally, board thermocouple data. Compare peak temperature, time above liquidus (TAL), and ramp rate against the solder paste manufacturer's recommended profile. If they ran a generic profile without profiling your specific board, the tombstoning could have a thermal component too.
Most CMs will send these on request — it's standard process data, not anything proprietary. Having the AOI data in particular lets you separate design issues from process issues without guessing.
For your layout review before the next order, the PCB design for manufacturability article has a section on paste layer rules and copper balancing that maps directly to what you're seeing here.
If you've got multiple boards from this build, rework the affected ones for functional testing while you sort out the root cause. No point waiting if the rest of the board is working.