Why Does an LDO Need a Minimum Output Capacitor ESR to Stay Stable?

Detailed Explanation

An LDO regulates its output using a feedback loop: an error amplifier compares a fraction of the output voltage against an internal reference and adjusts a pass transistor to hold the output at the target voltage. Like any feedback loop, this needs adequate phase margin across its bandwidth to avoid oscillating, and the loop's frequency response depends on more than just the LDO's internal compensation. The output capacitor is part of that loop, and its equivalent series resistance (ESR) shapes the response alongside its capacitance.

On many bipolar-process or older LDO designs, the output capacitor's ESR is not incidental: the LDO's internal compensation was designed assuming the capacitor contributes a specific zero to the loop response, at a frequency set by the capacitor's ESR and capacitance together. That zero cancels a pole elsewhere in the loop and is what keeps the phase margin adequate near the crossover frequency. Take the ESR out of that expected range, and the zero moves or disappears, and the phase margin the design relied on goes with it. See capacitor types and selection for how ESR itself varies by capacitor construction; that variation is exactly what causes this failure mode.

Practical Examples

A design uses an LDO whose datasheet specifies a minimum output capacitor ESR of several hundred milliohms, satisfied on the original prototype by a tantalum capacitor. A later revision swaps that tantalum capacitor for a ceramic capacitor of the same nominal capacitance to reduce cost and improve high-frequency bypassing, without checking the ESR requirement. The ceramic capacitor's ESR is far below the tantalum's, the loop's stabilising zero disappears, and the board that worked reliably on the original design now shows sustained oscillation on the regulator output, sometimes only under certain load or temperature conditions rather than continuously.

A different design uses an LDO explicitly specified as stable with any output capacitor ESR from zero upward, including ceramic. The same substitution from tantalum to ceramic changes nothing about loop stability, because that part's internal compensation was designed not to depend on the capacitor's ESR in the first place.

Design Considerations

• Check the specific part's stability requirement before assuming ceramic is always safe, or always risky. Neither is universally true; it depends entirely on how that specific LDO's compensation was designed. A part explicitly marketed as ceramic-capacitor-stable or cap-free doesn't need an ESR zero; an older or bipolar-process part very often does.
• Read the datasheet's stability region, not just a single recommended capacitor value. Where a datasheet plots stability as a region across ESR and capacitance, confirm your actual chosen capacitor, at its real DC-bias-and-temperature-derated ESR and capacitance, falls inside that region rather than just matching the single example value.
• Account for ESR's own temperature dependence when the capacitor is electrolytic or tantalum. ESR on these types increases substantially at low temperature, which can push a design that's stable at room temperature into a different, sometimes worse, part of the stability region at cold temperature. See capacitor types and selection for typical ESR-versus-temperature behaviour by capacitor type.
• Treat a capacitor substitution during a design revision as a stability re-check, not a drop-in swap. Cost reduction, footprint reduction, or supply-chain substitutions that change capacitor type or vendor can silently change ESR even when the nominal capacitance value stays the same.
• Power rail design and stability verification: choosing the right regulator topology and confirming loop stability under real board and thermal conditions is part of professional PCB design, not something to leave to a bench observation alone.

Common Mistakes

• Substituting a low-ESR ceramic capacitor for a datasheet-specified tantalum or electrolytic capacitor on an ESR-dependent LDO without checking the stability requirement, then treating the resulting oscillation as a mysterious or intermittent hardware fault.
• Assuming every modern LDO is ceramic-stable by default, when many parts, including some still in active production, still specify a minimum ESR range and are not stable with a bare low-ESR ceramic capacitor.
• Reading only the datasheet's single recommended capacitor example instead of the full stability region, and missing that a different capacitance value at the same nominal ESR falls outside the stable range.
• Diagnosing LDO oscillation as an unrelated noise or layout problem before checking output capacitor ESR against the datasheet's actual stability requirement, which is a common misdiagnosis given how similar the symptoms can look to a layout-driven noise issue.