How Do You Select a TVS Diode for ESD and Transient Protection on I/O Lines?

Detailed Explanation

Every connector on a product is a path for the outside world to inject a transient into the board: a person touching a USB port, a cable being hot-plugged, a relay switching nearby, or a lightning-induced surge on a long cable run. A TVS (transient voltage suppression) diode is the component most designs rely on to absorb that event before it reaches sensitive logic. For the underlying semiconductor behaviour and how a TVS compares to a Zener or rectifier diode, see what is a diode?. This page covers the selection decision itself: which parameters actually matter, how to size them against a specific I/O line, and where a TVS array IC is the better choice over a discrete part.

Getting TVS selection wrong shows up in two very different ways. Undersizing standoff voltage or clamping voltage lets a transient through to damage the protected IC, or causes the TVS itself to fail. Oversizing capacitance on a fast signal line degrades the eye diagram enough to cause intermittent data errors that have nothing to do with ESD at all, a failure mode that's much harder to trace back to the protection component than an outright ESD failure. See what is EMC immunity testing? for how ESD immunity is formally verified under IEC 61000-4-2, and how a TVS's placement and sizing feed directly into whether a product passes on the first attempt.

Standoff Voltage vs Clamping Voltage: The Two Numbers That Matter Most

A TVS datasheet leads with several voltage parameters, but two of them drive the selection decision:

• Standoff voltage (V_WM, also called working voltage): the maximum voltage the TVS can sit at continuously without conducting. The TVS must stay below this threshold during every normal operating condition. Otherwise it becomes a permanent, unwanted load on the rail.
• Clamping voltage (V_C): the voltage across the TVS while it's actively conducting the rated peak pulse current (I_PP). This is the voltage the protected IC actually sees during a transient event.

These two numbers pull in opposite directions, and the selection process is really about finding a part where both land in the right place for a specific line:

1. Set the standoff voltage above the line's worst-case normal operating voltage: the highest value it reaches once supply tolerance, ripple, and expected transient overshoot are accounted for. A commonly applied margin is at least 10% above that worst case, though the right figure depends on how tightly regulated the rail is.
2. Check that the resulting clamping voltage, at the TVS's rated peak pulse current, stays below the protected IC's absolute maximum voltage rating from its datasheet, with margin, since real ESD events don't always match the exact test current a datasheet's clamping voltage is specified at.

A 5 V logic rail with an absolute maximum input rating of 6 V, for example, needs a TVS with a standoff voltage safely above 5 V (accounting for rail tolerance) and a clamping voltage that stays under 6 V at the rated pulse current, a narrower window than it first appears, which is why general-purpose 5.5 V or 6 V standoff parts are common choices for 5 V and 3.3 V logic protection.

Junction Capacitance and High-Speed I/O Lines

Every TVS diode adds parasitic capacitance to the line it protects. On slow signals (a GPIO, a button input, a low-speed I2C bus) a few picofarads to tens of picofarads makes no practical difference. On high-speed differential or single-ended data lines, that same capacitance becomes a real signal-integrity problem: it rounds off edges, degrades the eye diagram, and can push a marginal link into intermittent errors that look nothing like an ESD failure.

As a rough guide to how much headroom a given interface has:

• USB 2.0 High Speed (480 Mbps): capacitance in the sub-picofarad to low-picofarad range is generally workable; several picofarads starts to measurably degrade the eye.
• USB 3.x SuperSpeed, HDMI, Ethernet (1 Gbps+): these interfaces need dedicated low-capacitance ESD array parts, typically specified under 1 pF per channel. Nexperia's PRTR5V0U2X, for example, is a dual-channel array datasheet-rated around 0.35 pF per line.
• Slow I/O (GPIO, analog sensor lines, low-speed serial buses): capacitance in the tens of picofarads range is usually acceptable, and a general-purpose TVS array is the simpler, lower-cost choice.

The practical rule: match the TVS family to the signal speed, not just the voltage. A part chosen purely because its standoff and clamping voltages look right can still be the wrong choice for a SuperSpeed or Gigabit-class line if its capacitance figure was never checked against the interface's bandwidth requirement.

Unidirectional vs Bidirectional TVS Selection

• Unidirectional TVS diodes conduct in one direction only, behaving like a normal diode in the forward direction and clamping like a Zener in reverse. They suit DC rails and signals that never go negative relative to ground: a 5 V or 3.3 V supply rail, or a single-ended digital output that idles high or low but never swings below ground.
• Bidirectional TVS diodes clamp symmetrically in both directions. They're required for any line that legitimately swings negative or is AC-coupled: differential data pairs (USB D+/D–, CAN_H/CAN_L, RS-485), audio lines, and any signal referenced to a floating or bipolar rail.

Using a unidirectional part on a line that can go negative clips the negative excursion as if it were a fault, corrupting the signal even under normal operation. Using a bidirectional part where a unidirectional one would do isn't functionally wrong, but it typically comes with a higher clamping voltage for a given standoff voltage compared to an equivalent unidirectional part, since the bidirectional construction has to support breakdown behaviour in both directions.

TVS Diode Arrays vs Discrete TVS Diodes

Most modern designs default to a multi-channel TVS array IC rather than individual discrete TVS diodes on each line, for good reason:

• Array ICs integrate several protected channels (commonly 2 to 8) sharing a single ground connection, in one small package placed right at the connector. USB, HDMI, and general digital I/O headers are typically protected this way: one part covers D+, D–, and often CC or power lines in a single footprint.
• Discrete TVS diodes remain the better choice for individual high-power lines: a single power input, a motor driver output exposed to inductive kickback, or any line where the expected surge energy (per IEC 61000-4-5, on long cable runs) exceeds what a compact array IC is rated to absorb. Discrete parts in larger packages (DO-214, SMB, SMC) offer higher peak pulse power ratings than array ICs, at the cost of one part per line instead of one part per connector.

The decision usually comes down to channel count and energy: a connector carrying several similar-voltage, similar-risk signal lines is a natural fit for an array IC; a single line carrying disproportionate surge energy (a mains-adjacent input, a long field-wiring run) is a natural fit for a discrete part sized specifically for that energy level.

Board Placement and Grounding

Where the TVS sits on the board matters as much as which part is chosen. The discharge current from an ESD event needs the shortest, lowest-inductance path available, or it will find another one: through adjacent traces, through the IC's own package, or through whatever offers the least impedance at the transient's rise time (under a nanosecond, per IEC 61000-4-2).

• Place the TVS as close to the connector pin as the footprint allows, before any series resistor, ferrite bead, or other passive component on that line. Anything placed between the connector and the TVS gives the fast edge a length of unprotected trace to couple into neighbouring signals before it's clamped.
• Keep the ground return short and low-inductance. A long or narrow trace from the TVS's ground pin back to the reference plane adds inductance that raises the effective clamping voltage the protected IC sees, even if the TVS's own datasheet clamping voltage looks adequate on paper. A direct via to a solid ground plane, right at the TVS footprint, is the standard approach.
• Route the protected line directly from connector to TVS to the rest of the circuit, with no stub or branch off that path. A stub is a discontinuity the fast ESD edge can reflect off, reducing how effectively the TVS clamps it.

For the broader chassis-grounding and return-path practices that support this (solid ground planes, short high-current loops), see how do you reduce EMI in PCB design?.

Design Considerations

• Size standoff voltage and clamping voltage against the specific line, not a generic default. A 5 V rail and a 3.3 V rail need different parts even if both fall under "logic protection". Check the actual worst-case operating voltage and the actual IC's absolute maximum rating for each.
• Treat capacitance as a first-order parameter on any interface above a few hundred Mbps. USB 3.x, HDMI, Ethernet, and similar high-speed interfaces need array parts specifically rated for low capacitance; a general-purpose TVS selected on voltage alone can silently degrade signal integrity on these lines.
• Default to an array IC at the connector for multi-line digital and USB-class ports, and reserve discrete TVS diodes for single lines carrying disproportionate surge energy, per the array-vs-discrete trade-off above.
• Design the ground return path in from the schematic stage, not after layout. A short, dedicated via from the TVS ground pin to a solid plane is a schematic-level decision that becomes much harder to retrofit once the board is routed. Zeus Design's PCB layout service includes ESD and transient protection placement, ground return design, and impedance-controlled routing as part of PCB design engagements headed toward EMC compliance testing.
• Confirm peak pulse power against the expected event, not just clamping voltage. IEC 61000-4-2 ESD events are fast but low-energy; IEC 61000-4-5 surge events on long cable runs are much higher-energy. A TVS sized correctly for ESD duty at a connector can still be undersized for a surge event on the same line if the line also runs any distance outside the enclosure. See what is EMC immunity testing? for how the two test methods differ.

Common Mistakes

• Setting standoff voltage too close to the rail's nominal voltage. Once supply tolerance and the TVS's own breakdown tolerance overlap, the TVS begins conducting during normal operation, showing up as unexplained leakage current or gradual heating rather than an obvious failure. Leave real margin above the worst-case operating voltage, not just the nominal value.
• Selecting a TVS on voltage alone and ignoring capacitance on a high-speed line. A part with perfect standoff and clamping voltage figures can still be the wrong choice for a USB 3.x, HDMI, or Gigabit Ethernet line if its capacitance wasn't checked against the interface's bandwidth. The failure this produces (intermittent data errors) rarely gets traced back to the protection diode without deliberate investigation.
• Using a unidirectional TVS on a line that swings negative. Differential pairs, AC-coupled signals, and anything referenced to a bipolar or floating rail need a bidirectional part; a unidirectional TVS clips the negative half of the signal as if it were a transient event.
• Placing the TVS after a series resistor or ferrite bead instead of right at the connector. Any passive component between the connector and the TVS gives the ESD edge unprotected trace length to couple energy into adjacent signals before the clamp engages.
• Skimping on the ground return path. A long or high-inductance trace from the TVS's ground pin to the reference plane raises the effective voltage the protected IC sees during a transient, even when the TVS itself is correctly specified. The clamp is only as good as the path carrying the discharge current away.
• Sizing for ESD alone on a line that also needs surge protection. A connector-facing TVS correctly sized for IEC 61000-4-2 ESD duty can be undersized for an IEC 61000-4-5 surge event if that same line runs any distance outside the enclosure. Long cable runs need the peak pulse power rating checked against the surge waveform, not just the ESD event.