How Do MOSFET Gate Driver ICs and Bootstrap Circuits Work?

Detailed Explanation

A power MOSFET or IGBT's gate looks electrically like a capacitor. Turning the device on or off means charging or discharging that capacitance, and how fast that happens determines the switching loss, the electromagnetic emissions, and — in a half-bridge — whether the high-side and low-side devices ever conduct at the same time. A gate driver IC exists to move that charge quickly, and in circuits where the switch's source terminal isn't fixed at ground, to do it from a supply that floats with the switch.

Why a GPIO Isn't Always Enough

A microcontroller GPIO can source or sink a few mA to a few tens of mA continuously, but a MOSFET's gate doesn't need continuous current — it needs a large peak current for a very short time during each switching transition, then essentially none while fully on or fully off (see What Is a Transistor? for the underlying gate charge, Qg, concept).

At 500 kHz with a total gate charge Qg = 20 nC, the average gate current is only Qg × f = 10 mA — well within GPIO capability. But that charge has to move in the tens-of-nanoseconds transition time, not spread evenly across the cycle. A transition completing in 20 ns requires a peak current of roughly Qg / t = 1 A — three orders of magnitude above what a GPIO can deliver. A GPIO-driven gate under these conditions charges slowly, spends more time in the linear region during each transition, and dissipates far more switching loss in the MOSFET than the same device driven by a proper gate driver.

As a rule of thumb, dedicated gate drive becomes necessary once switching frequency exceeds roughly 100 kHz, gate charge is large (high-current power MOSFETs commonly have Qg in the tens to hundreds of nC), or — regardless of frequency — the device sits on the high side of a half-bridge.

Low-Side vs High-Side Drive

Low-side drive is the simple case: the MOSFET's source is at (or near) ground, so the gate drive signal only needs to swing between ground and a fixed positive rail. A gate driver IC here still helps at higher frequencies by supplying the peak current a GPIO cannot, but the reference point for the drive signal never moves.

High-side drive is harder. In a half-bridge (the switching cell inside a synchronous buck converter, a boost converter, a motor phase leg, or a Class D amplifier), the high-side MOSFET's source is connected to the switching node — the junction between the two switches — which itself swings from close to ground to close to the input rail every switching cycle. The gate must be driven roughly VGS above whatever voltage the source happens to be at that instant, meaning the drive circuit's reference point moves with the switching node. A drive signal referenced to system ground cannot do this directly.

How a Half-Bridge Gate Driver IC Works

A half-bridge gate driver IC (e.g. the IR2110/IR2113 family, TI's UCC27211/UCC27201, or an isolated part like the Si8233 or ADuM4135 for higher-voltage or higher-noise applications) solves the high-side problem with two independent output stages:

• A low-side driver, referenced to ground, drives the low-side MOSFET directly.
• A high-side driver, referenced to the switching node (often labelled VS or SW), drives the high-side MOSFET. Its own local supply rail — labelled VB or BST — sits a fixed voltage above VS, so its output can swing between VS and VS + VGS regardless of where VS itself currently sits.

The high-side driver's floating local supply is almost always provided by a bootstrap capacitor, described below, rather than a second isolated power supply — bootstrap drive is cheaper and simpler for the vast majority of designs, and is why gate driver ICs are frequently called "bootstrap gate drivers."

Bootstrap Capacitor and Diode Design

The bootstrap circuit is a capacitor (CBOOT, connected between the driver's VB and VS/SW pins) charged through a diode (DBOOT) from a low-voltage bias rail (often VCC or a dedicated 12-15V rail), while the switching node (and therefore VS) is pulled low by the low-side MOSFET being on.

How it charges: when the low-side switch is on, VS is near ground, so the diode is forward-biased and charges CBOOT up to roughly VCC minus the diode's forward drop. When the high-side switch turns on, VS jumps up to near the input rail — the diode becomes reverse-biased (blocking the low-voltage rail from being pulled up with it) and CBOOT, now floating, supplies the high-side driver's current from its own stored charge for the duration of the high-side on-time.

Sizing the capacitor: CBOOT must supply the high-side driver's quiescent (IC operating) current plus the gate charge/discharge current for every switching event during the high-side switch's maximum on-time, without its voltage drooping below the driver's undervoltage lockout (UVLO) threshold. A commonly used starting-point sizing equation from gate driver application notes is:

C_BOOT ≥ (Q_gate + I_QBS × t_on(max)) / ΔV_BOOT

Where Q_gate is the high-side MOSFET's total gate charge, I_QBS is the driver's high-side quiescent current, t_on(max) is the longest expected high-side on-time (worst case at minimum switching frequency and maximum duty cycle), and ΔV_BOOT is the allowable droop — typically kept to a small fraction of a volt, well clear of the driver's UVLO threshold. Manufacturer application notes (see references below) generally recommend adding a safety margin — commonly by using several times the value the equation produces — because the equation doesn't account for capacitor tolerance, ESR, or leakage. A typical value for a several-hundred-kHz buck converter driving a moderate-Qg MOSFET is in the range of tens to a few hundred nanofarads; low-ESR ceramic capacitors (X7R, rated well above the bootstrap rail voltage) are standard.

Bootstrap diode: must block the full input/bus voltage when reverse-biased (VS at its highest point) and should have fast, soft reverse recovery — a slow-recovery diode injects reverse current into the bootstrap node during the low-to-high transition, adding loss and noise. Ultrafast recovery diodes with reverse recovery time under ~100 ns are standard; some gate driver ICs integrate the bootstrap diode, removing this as a discrete design decision.

The refresh requirement: because the bootstrap capacitor only recharges while the low-side switch is on, a half-bridge stuck at a very high duty cycle (high-side almost always on) or a very low switching frequency can leave insufficient time to refresh CBOOT before it droops into UVLO. This is why many half-bridge topologies (including synchronous buck converters used as pure DC-DC point-of-load regulators) specify a maximum duty cycle, and why 100% duty cycle drive of the high side is not achievable with a bootstrap-supplied driver — a separate isolated or charge-pump supply is required if true 100% high-side duty cycle is needed.

Propagation Delay and Dead-Time

Gate driver ICs specify propagation delay — the time from the input logic transition to the output gate voltage responding — typically in the tens of nanoseconds, and matching between the high-side and low-side propagation delays, since a mismatch shifts the effective switching instant of one device relative to the other.

Dead-time is the deliberate gap inserted between one switch turning off and the other turning on, ensuring the two devices in a half-bridge are never both conducting at once (shoot-through), which would create a near-short-circuit across the bus and can destroy both devices within microseconds. Dead-time must be long enough to guarantee the outgoing switch has fully turned off (accounting for its actual turn-off time, not just the driver's propagation delay) but short enough to avoid excessive body-diode conduction loss in a synchronous topology, where the complementary device's body diode carries the load current during the dead-time gap. Some gate driver ICs and dedicated half-bridge controllers set dead-time internally (often adaptively, sensing the switching node); others require it to be configured by the controlling MCU or PWM controller.

Common Gate Driver ICs

Isolated drivers (Si8233, ADuM4135 and similar) replace the bootstrap capacitor with a galvanic isolation barrier — see Optocoupler vs Digital Isolator for how isolated gate drive relates to the wider isolation-technology decision, including the CMTI rating that matters for fast-switching GaN/SiC gate drive. Isolated drivers avoid the bootstrap refresh/duty-cycle limitation entirely and are the standard choice for high-voltage bus designs (typically above a few hundred volts) or where the high-side and low-side circuits need full galvanic separation rather than just level-shifting.

For a synchronous buck converter, which is the most common design that puts this bootstrap circuit into practice, see How Does a Buck Converter Work? and Buck Converter PCB Layout for the physical placement rules that keep the bootstrap loop's parasitic inductance low.

Design Considerations

• Match the driver's peak current to the MOSFET's gate charge and desired transition time. A driver rated for 1A peak output current charging a MOSFET with Qg = 20 nC in 20 ns needs roughly Qg / t = 1A — right at the driver's limit. Choose a driver with headroom above the calculated requirement, not exactly at it.
• Keep the bootstrap loop physically tight. The loop formed by the bootstrap capacitor, the bootstrap diode, and the driver's VB/VS pins carries fast-changing current during recharge; excess trace inductance in this loop causes ringing that can exceed the driver's absolute maximum VB-VS rating. Place the bootstrap capacitor as close as possible to the driver IC.
• Account for gate resistor asymmetry when tuning switching speed. A larger turn-on gate resistor slows dv/dt and reduces switching noise at the cost of higher switching loss; a smaller turn-off gate resistor (often achieved with a parallel diode bypassing the resistor on turn-off) speeds discharge without adding turn-on noise. Many practical half-bridge designs use asymmetric turn-on/turn-off resistor networks for this reason.
• Verify UVLO thresholds against your minimum operating voltage. Both the low-side (VCC) and high-side (VB-VS) UVLO thresholds must be comfortably below your actual operating rail — a driver that browns out during a supply dip can leave a MOSFET partially enhanced in a high-loss state rather than cleanly off.

Common Mistakes

• Omitting or undersizing the bootstrap capacitor's refresh margin at low switching frequency. A design validated at the nominal switching frequency can fail at a lower frequency (e.g. during soft-start, light-load frequency foldback, or a fault condition that stretches the switching period) because the bootstrap capacitor has more time to droop between refresh events. Check CBOOT sizing against the lowest switching frequency the converter can actually reach, not just the nominal operating point.
• Using a standard PN diode as the bootstrap diode. Slow reverse recovery injects charge back into the bootstrap node and increases loss at the switching node transition; use a fast or ultrafast recovery diode rated for the full bus voltage, or a driver IC with an integrated bootstrap diode.
• Setting dead-time too short to save on synchronous rectification loss. Insufficient dead-time causes shoot-through — both switches briefly conducting together — which shows up as excessive input current draw, MOSFET overheating, or catastrophic failure under load. Verify dead-time against the outgoing switch's actual turn-off time (including gate driver propagation delay and the MOSFET's own turn-off delay), not just the controller's default setting.
• Ignoring the maximum achievable duty cycle with a bootstrap-supplied driver. A control loop that commands close to 100% high-side duty cycle (attempting to minimise the low-side switch's on-time) starves the bootstrap capacitor of refresh time. If the application genuinely requires very high or 100% duty cycle, use an isolated driver or a charge-pump-supplied high-side driver instead of a bootstrap topology.
• Driving a large-Qg MOSFET directly from a PWM controller's integrated low-current driver. Many PWM controller ICs include a modest integrated gate driver intended for small- to medium-Qg MOSFETs at moderate frequency. Pairing one with a high-Qg power MOSFET at high frequency exceeds the controller's drive capability — add an external gate driver stage between the controller and the MOSFET.