How Should You Lay Out a Buck Converter PCB?

Detailed Explanation

In a linear regulator, PCB layout is relatively forgiving — it mostly affects thermal performance and noise on the output. In a buck converter, layout directly determines EMI, efficiency, and output voltage quality. A well-designed regulator on a poor PCB layout will fail EMC pre-compliance; the same IC on a carefully laid out board will pass. Component selection and layout must be addressed together.

Understanding how a buck converter works — the two switching phases, the inductor current continuity, the duty cycle relationship — is the foundation for understanding why each layout rule exists. The rules are not arbitrary; they follow directly from the physics of a switching loop.

The Switching Loop: Why It Is the Starting Point

When the high-side switch closes, current flows from the input capacitor through the switch, through the inductor, to the load, and back through GND to the input capacitor. When the switch opens, the inductor forces current to continue through the low-side switch (in a synchronous converter) or catch diode (in an asynchronous converter). These transitions create high-frequency current pulses in the loop formed by the input capacitor, the switching element, and the inductor.

This switching loop is the primary source of radiated EMI in a buck converter. The loop acts as a small magnetic antenna — a loop antenna — and the radiated field is proportional to the loop area and the rate of current change (dI/dt). Minimising the physical area enclosed by this loop is the single most important thing you can do in layout. Everything else follows from that.

Rule 1 — Place the Input Capacitor First and Closest

The input capacitor handles the pulsed current demand from the switching elements. When the high-side switch fires, it draws a pulse of current from the input; the input cap absorbs that pulse locally, keeping the input voltage stable. If the input cap is placed far from the IC, the trace inductance between them means the current pulse has to travel a longer path before it reaches the cap, increasing switching loop area and input voltage ringing.

Place the input capacitor — or at minimum one of the input capacitors if you're using multiple — as close as possible to the IC's Vin and GND pins. On a two-layer board this means immediately adjacent; on a four-layer board, the GND return from the cap to the IC GND pin should be as short as the top-layer placement allows.

Use low-ESR ceramic capacitors (X5R or X7R dielectric) for the input bypass role. Electrolytic or tantalum capacitors have too much ESR and inductance to absorb the fast switching pulses; they're acceptable as bulk capacitance farther from the IC, but not as the primary input bypass.

Rule 2 — Keep the SW Node Copper Area Small

The switch node (SW pin of the IC, or the drain of the high-side FET in a discrete design) toggles between Vin and GND at the switching frequency. This makes it the loudest node in the circuit. Any copper connected to the SW node acts as an antenna radiating at the switching frequency and its harmonics.

The SW node copper should be exactly large enough to connect the IC's SW pin to the inductor input pin — and no more. Do not run a pour, fill, or large copper island on the SW node. Do not add thermal vias through the SW node copper (thermal dissipation belongs at the exposed pad/GND node, not the switch node). Do not route other signals beneath or adjacent to the SW node copper on adjacent layers.

The contrast with the power and ground plane design rules for other power nodes is intentional: power planes are good for distributing stable DC voltages, but a switching AC voltage like the SW node should be kept confined and small, not spread into a plane.

Rule 3 — Maintain a Solid Ground Plane Under the Regulator

Return current in the ground plane flows directly under the signal traces above it, following the path of least impedance. If there is a slot, split, or void in the ground plane under the switching loop, return current is forced to detour around the gap — effectively increasing the switching loop area even if the top-layer routing looks compact.

Keep the ground plane continuous and unbroken under the entire power stage: IC, input capacitor, inductor, and output capacitor. On a two-layer board, use a solid copper pour on the back side with frequent via stitching back to the top-side GND connections. On a four-layer board, Layer 2 (immediately below the component layer) should be an uninterrupted GND plane in the regulator area.

This is the same principle that underlies general PCB ground plane design, but it's more critical here because the return currents are switching at high frequency.

Rule 4 — Place the Output Capacitor Close to the Inductor

The output capacitor is less critical than the input capacitor from an EMI standpoint — by the time current reaches the output side, the inductor has smoothed most of the switching pulses. But the output cap's GND connection should return directly to the IC's GND pin, not detour through a long trace, to avoid adding impedance into the output voltage sensing path.

For output capacitors, ceramic (X5R/X7R) capacitors give the lowest ESR and are preferred for the primary output filtering role. Be aware of DC bias derating — a 10 µF 10V X5R capacitor may only have 3–4 µF effective capacitance at 5V output due to the capacitance vs voltage curve of ceramic dielectrics. This is the same phenomenon that affects decoupling capacitor placement and selection. Account for this when calculating effective output capacitance — DC bias derating was the root cause of the output voltage sag in the TPS63020 4-switch buck-boost bring-up thread, where 4V-rated 22 µF 0402 X5R capacitors delivered only ~10 µF actual at 3.3V output.

Rule 5 — Route the Feedback Divider Away from the Switch Node

The feedback divider (two resistors from output to FB pin to GND) sets the regulated output voltage. The IC continuously senses the FB pin voltage to close the control loop. Any switching noise coupled into the FB pin appears as error in the sensed output voltage, causing the control loop to respond unnecessarily — which degrades output ripple, can cause instability, and is difficult to filter out after the fact.

Place the feedback divider physically close to the FB pin of the IC, on the opposite side of the IC from the SW node if possible. Route the FB trace short and away from the SW node copper. The bottom resistor of the divider (from FB to GND) should have its GND connection close to the output capacitor's GND, not to the switching GND island — this ensures the feedback reference is the quiet output GND, not the switching ground.

Thermal Management

Integrated buck regulators (a single IC with internal power FETs, e.g. TPS62xxx, LM2596, MP2307) dissipate power through the package's exposed pad (EP), which is usually connected internally to GND. Solder the EP to a copper pad on the PCB and add a thermal via array under the pad to carry heat to the inner GND planes. More copper area around the IC means lower thermal resistance — add polygon pours on accessible layers connected to GND under and around the IC.

Do not place the EP thermal via array in the SW node copper. The exposed pad in a correctly packaged integrated buck IC is GND, not SW — confirm in the datasheet. Putting thermal vias in the SW copper would couple switching noise into the GND plane.

Discrete designs (a separate controller IC plus external high-side and low-side FETs) give more layout flexibility but require more care:

• The high-side FET source is connected to SW — its thermal pad (if present) is at switch-node potential, so its thermal via array must connect to the compact SW copper, not the GND plane.
• The low-side FET source is GND — its thermal vias go directly to GND plane.
• The bootstrap capacitor (BST pin, used to drive the high-side gate) must be placed close to the controller's BOOT pin and connected between BOOT and SW. Long bootstrap traces add inductance that slows high-side gate turn-on and reduces efficiency.

Integrated vs Discrete Design Layout Differences

An integrated regulator constrained its power stage to the IC package — you cannot change the internal switch node or FET placement. The layout task is placing the IC, input cap, inductor, and output cap as close and compact as possible, then getting the exposed pad and GND plane right. The IC datasheet's recommended layout should be followed closely; it was designed around the specific internal parasitics of that IC.

A discrete design gives you control over where the FETs and driver sit. The high-side FET drain, high-side FET source (= SW), and low-side FET drain should form a compact triangle — the switch node area between the high-side source and low-side drain is the hot loop and should be minimised just as for an integrated design.

If your product design will include a switching power supply and you want the layout reviewed or designed to minimise first-spin EMC issues, Zeus Design's PCB design service covers power-dense and switching supply layouts with EMC in mind from the outset.

Design Considerations

The rules above are universal, but their relative importance shifts with design parameters:

• Higher switching frequency (1–3 MHz) → layout quality matters more, edges are faster, loop inductance is more destructive. Smaller components help (smaller caps, smaller inductor) which naturally encourages tighter layout.
• Higher output current → larger trace widths required (see PCB trace width and current capacity), larger thermal via arrays, potentially more input and output capacitors in parallel.
• High-voltage designs (>30V input) → component creepage and clearance requirements interact with the tight layout preferred for EMI; check IPC-2221 for appropriate spacings.
• Mixed-signal boards → keep the switching regulator power island physically separated from sensitive analog and RF circuitry, with GND plane continuity maintained but the layout designed so return currents from the switcher don't flow under the analog section. For the RF section specifically, RF PCB layout guidelines cover the antenna keepout zone, 50 Ω microstrip rules, and ground plane requirements that apply once the switcher boundary is established.

Common Mistakes

• Large switch node copper area: adding a copper pour or fill to the SW node to "clean it up" or make the layout look symmetrical is one of the most common errors. The SW node is a radiating antenna; extra copper makes it worse, not better.
• Input capacitor placed after the inductor or far from the IC: the input cap closes the fast switching current loop — if it's not physically the closest component to the IC's Vin and GND pins, the loop area grows and EMI increases disproportionately.
• Slots or routing channels through the GND plane under the switcher: any gap in the ground plane forces return current to detour, increasing the effective switching loop area even if the top-layer layout looks compact. Common causes: routing signal traces through the plane island, or splitting the plane for unrelated reasons.
• Thermal vias through SW node copper: placing a via array under the exposed pad without first confirming whether the EP is GND or SW. In integrated buck ICs the EP is almost always GND; adding thermal vias to GND planes here is correct. Putting thermal vias in SW copper couples switching noise into the plane.
• Feedback divider trace running near the inductor or switch node: high-impedance FB traces that route close to the SW copper pick up capacitively coupled noise, causing output ripple or control-loop instability that is very difficult to diagnose without an oscilloscope on the FB pin.
• Copying a reference design layout at a different switching frequency: the reference layout's component spacing is tuned to the specific IC's internal parasitics and the reference components; at a different frequency, different components, or a different board stack-up, the same layout may produce unexpected EMI or instability.