How Does a Buck Converter Work?

Detailed Explanation

A buck converter is the most common switching power supply topology. It appears in virtually every embedded system that needs to step a supply rail down — from a 12V input to a 3.3V microcontroller rail, or from a 5V USB input to a 1.8V processor core supply.

The Four Core Components

Every buck converter is built around the same four elements:

How the Switching Cycle Works

Phase 1 — Switch ON (duration: ton)

The high-side MOSFET closes. The full input voltage Vin appears at the "switching node" (the junction of the switch, inductor, and diode). With Vin > Vout, the voltage across the inductor is positive (Vin − Vout), so inductor current ramps up at:

ΔIL/Δt = (Vin − Vout) / L

Energy flows from the input source into the inductor's magnetic field and onward to the output capacitor and load. The freewheeling diode is reverse-biased and carries no current.

Phase 2 — Switch OFF (duration: toff)

The MOSFET opens. The inductor opposes the sudden change in current — its stored magnetic field collapses, reversing the voltage at the switching node. This forward-biases the freewheeling diode (or turns on the low-side synchronous MOSFET), allowing inductor current to continue circling through the diode and back to the inductor. Current ramps down at:

ΔIL/Δt = −Vout / L

The output capacitor supplies the load during the intervals when the inductor current is insufficient alone.

Volt-Second Balance: Why Vout = Vin × D

In steady state, the inductor current must return to the same level at the end of every switching cycle. This means the volt-seconds applied across the inductor during ton must exactly equal the volt-seconds removed during toff:

(Vin − Vout) × ton = Vout × toff

Since D = ton / T and (1 − D) = toff / T, this simplifies to:

Vout = Vin × D

This is the ideal volt-second balance. At D = 0.275, a 12V input produces 3.3V. At D = 0.66, a 5V input produces 3.3V. A feedback loop — voltage divider from the output → error amplifier → PWM comparator — continuously adjusts D to hold the programmed output against load and line variation.

Continuous vs Discontinuous Conduction Mode

Continuous Conduction Mode (CCM) is the normal operating condition at typical loads. The inductor current never reaches zero — it rides as a triangular ripple on top of a positive average current equal to the load current. The steady-state transfer function Vout = Vin × D applies directly in CCM.

Discontinuous Conduction Mode (DCM) occurs at light loads. If the inductor current would reach zero before the next cycle starts, the freewheeling diode blocks reverse current, inductor current sits at zero for the remainder of the period, and the inductor rings with parasitic capacitance. DCM is not a failure — it happens naturally at light load in most designs and some converters are specifically designed to operate in DCM for improved light-load efficiency (the control law changes slightly but the converter remains stable).

The boundary between CCM and DCM is:

Iload(boundary) = ΔIL / 2 = (Vin − Vout) × D / (2 × f × L)

Below this current, the converter enters DCM.

Key Design Parameters

Switching frequency (f) — Higher frequency shrinks the required inductor and capacitor values (both scale roughly as 1/f), but increases switching losses in the MOSFET and core losses in the inductor. Typical integrated buck ICs switch at 100 kHz to 2 MHz. Very high-frequency designs (>2 MHz) enable tiny inductors but require careful layout and low-loss magnetics.

Inductor value — Sets the peak-to-peak current ripple:

ΔIL = (Vin − Vout) × D / (f × L)

A common rule of thumb is to target a ripple ratio of 20–40% of the rated load current. Smaller inductor → more ripple → larger output capacitor requirement. Larger inductor → less ripple but physically larger and slower transient response.

Output capacitor — Determines the output voltage ripple, which at moderate switching frequencies is dominated by the capacitor's Equivalent Series Resistance (ESR):

ΔVout ≈ ΔIL × ESR

Ceramic capacitors have very low ESR (a few milliohms) and are the preferred output capacitor for most buck converter designs today. Electrolytic capacitors have 10–100× higher ESR, which translates directly into higher output ripple unless paralleled with ceramics.

Efficiency is approximately:

η ≈ 1 − (Pswitch + Pcond + Pgate + Pcore) / Pin

• Switching losses (Pswitch): scale with Vin², f, and MOSFET gate/output capacitance — dominant at high frequency and high input voltage.
• Conduction losses (Pcond): I²R losses in MOSFET Rds(on) and inductor DCR — dominant at high current.
• Gate drive losses (Pgate): Qg × Vgs × f — usually minor but measurable at high frequency.

Synchronous vs Asynchronous Rectification

In an asynchronous (diode) buck, the freewheeling element is a Schottky diode. The Schottky forward voltage (typically 0.3–0.5V) produces a conduction loss of Vf × Iload × (1 − D) — significant at high current or low output voltage. At 3.3V and 3A with a 0.4V Schottky, the diode alone wastes about 1.2W.

A synchronous buck replaces the freewheeling diode with a second (low-side) MOSFET whose Rds(on) at the same current produces a much smaller voltage drop. A 10 mΩ FET at 3A drops only 30 mV — about 10× less loss than the equivalent Schottky. All integrated buck ICs rated above ~85% efficiency use synchronous rectification.

The controller must carefully prevent shoot-through — the brief overlap where both high-side and low-side FETs are simultaneously on, which would short Vin to ground. Modern controllers include programmable or adaptive dead-time circuits that insert a small gap (typically 10–50 ns) between one FET turning off and the other turning on.

Practical Examples

A 12V-to-5V, 2A buck converter using a TPS54231-style IC at 500 kHz:

• D = 5 / 12 = 0.417
• Target ripple ratio 30% → ΔIL = 0.6A
• L = (12 − 5) × 0.417 / (500k × 0.6) = 9.7 µH → use 10 µH
• Output capacitor: with ΔIL = 0.6A and ESR target < 20 mV ripple → ESR < 33 mΩ → two 22 µF ceramic capacitors in parallel (ceramic ESR ≈ 2–5 mΩ each) is typical

A 5V-to-1.8V, 0.5A rail for an MCU core: at D = 0.36 and 1 MHz, the inductor shrinks to ~2.2 µH and the whole converter can be designed to fit a 5×5 mm footprint with a micro-size package IC.

Design Considerations

• Inductor saturation current: the inductor must not saturate under peak current — which is Iload + ΔIL/2. When an inductor saturates, its inductance collapses, current spikes, and the MOSFET may fail. Always select an inductor whose saturation current rating exceeds the peak current by a comfortable margin (typically 1.2× minimum). See inductor types and saturation current for core material comparisons, DCR, and how to read an Isat specification correctly.
• Output capacitor placement: place output capacitors as close as possible to the load they decouple — voltage spikes during fast load steps will be absorbed by the inductance of any trace between the capacitor and load. See decoupling capacitor placement for placement principles that apply equally to buck output filtering.
• Switching-node layout: the switching node (between the high-side MOSFET drain, low-side MOSFET drain, and inductor) carries fast current transitions (high dI/dt) at high voltage (Vin). Keep this copper area small to minimise radiated EMI. The PCB power and ground plane design principles around return current paths and solid ground planes apply directly to switching-regulator layout.
• Feedback loop compensation: most buck controller datasheets provide a step-by-step procedure for calculating the Type II or Type III compensation network values for the error amplifier. Following this procedure — rather than simply copying a reference design for a different inductor/capacitor combination — prevents instability and poor transient response.
• Input capacitor: the input to a buck converter draws pulsed current at the switching frequency. An input capacitor (often 10–22 µF ceramic close to the FETs) must handle this RMS ripple current without excessive heating. Don't undersize it — most buck IC datasheets specify a minimum input capacitor.
• When to use a buck vs an LDO: if the input-to-output voltage drop is small (< 1.5V) and current is low (< 500 mA), a linear regulator is often simpler, quieter, and adequate — see linear vs switching regulator for a structured comparison. When the drop is large (e.g. 8.4V from a 2S pack to 3.3V) the LDO dissipates too much heat; the LDO overheating forum thread shows the calculation and the switch to a buck in practice.
• When to use a buck vs a buck-boost: if your input voltage can ever drop to or below your output voltage (for example, a single Li-ion cell → 3.3V rail), a buck alone cannot regulate across the full range — see how to choose a DC-DC converter topology for the full topology decision framework. The TPS63020 4-switch buck-boost bring-up thread shows the mode-transition instability and output capacitor derating issues that arise in practice when targeting the Li-ion → 3.3V crossing.
• Production power stage design: selecting the right inductor, MOSFET, compensation network, and layout for a commercial buck converter involves verifying efficiency curves, transient response, and EMC compliance — work Zeus Design's hardware team handles across a wide range of input/output specifications and regulatory requirements.

Common Mistakes

• Inductor saturation: choosing an inductor based on its nominal inductance value alone and ignoring the saturation current rating. An inductor that saturates under peak load becomes essentially a short circuit at that moment — frequently destroying the high-side FET.
• No input capacitor, or capacitor placed far from the FETs: the fast switching current loop (Vin → high-side FET → inductor → output) must be kept tight with the input bypass capacitor closing the loop locally. A long trace from the bulk capacitor adds inductance that produces ringing and EMI.
• Copying a reference design inductor value at a different switching frequency: the optimal inductor value scales inversely with frequency. A 10 µH inductor from a 300 kHz reference design used at 1 MHz will have very low ripple (good) but poorer transient response and may exhibit unexpected DCM behaviour at light load.
• High-ESR output capacitors without accounting for ripple: electrolytic capacitors are sometimes used for output bulk capacitance, but their ESR directly adds to output ripple. Without at least one low-ESR ceramic in parallel, the ripple can be far worse than the inductor current ripple alone would predict.
• Feedback resistor divider routing near the switching node: the feedback pin on most buck ICs is high-impedance. A feedback trace that runs close to the switching node, inductor, or other high-frequency signals will pick up noise, causing output voltage jitter. Route the feedback trace as a quiet, short, low-impedance path from the output filter directly to the IC.