What Is Ionic Contamination (SIR) Testing for PCB Assemblies?

Detailed Explanation

Flux does its job by chemically activating and removing oxides from the metal surfaces being soldered, which means the same activator chemistry that makes a good solder joint possible leaves ionic residue behind on the board afterward. Whether that residue matters depends entirely on how much is left, what kind of flux produced it, and what the finished product's operating environment and reliability requirements are. Ionic contamination testing exists to answer that question with a measurement rather than an assumption, since a board that looks visually clean can still carry enough residual activator to cause a field failure months or years later.

The two failure modes ionic contamination actually causes are electrochemical migration, where residual ions combine with moisture and an applied voltage bias to grow a conductive dendrite between adjacent conductors, eventually shorting them, and leakage current, where residual contamination lowers the effective insulation resistance between traces enough to disturb a sensitive high-impedance node even without an outright short. Both failure modes are moisture-dependent, which is why they tend to show up as intermittent, humidity-correlated field failures rather than a clean bench-test failure.

ROSE Testing

ROSE (Resistivity of Solvent Extract) testing is the fast, routine method: the assembled board (or a batch sample) is rinsed in a measured volume of an isopropanol-water solvent mixture, and the solvent's resistivity is measured before and after. Ionic residue dissolved off the board lowers the solvent's resistivity proportionally, and the result is compared against a pass/fail threshold, commonly expressed as an equivalent NaCl-contamination level per unit board area under IPC's test methodology. ROSE testing is quick (minutes, not days), doesn't require specialized comb-pattern test coupons, and is well suited to routine process-control screening on a production line, but it's a bulk measurement: it reports total ionic contamination without distinguishing between a genuinely corrosive activator residue and a relatively benign one, and it doesn't directly measure the electrical property (insulation resistance) that actually causes field failures.

SIR Testing

Surface Insulation Resistance testing, defined in IPC-TM-650 test method 2.6.3.3, measures the thing ROSE testing only infers: actual insulation resistance between two interdigitated comb-pattern conductors on a test coupon, processed through the same flux and reflow profile as the production board, then subjected to an extended bias voltage under elevated temperature and humidity (commonly around 85 percent relative humidity, tens of degrees Celsius, for multiple days) while insulation resistance is logged continuously. A flux or process that maintains adequate insulation resistance throughout that extended stress, without a downward trend indicating migration in progress, passes; a flux that degrades meaningfully over the test period fails, regardless of what a ROSE test on the same board might have shown.

SIR testing is slower and more involved than ROSE testing, which is why it's typically used to qualify a flux, a reflow profile change, or a no-clean process decision once, rather than performed on every production board. Once a flux and process combination has passed SIR qualification, ROSE testing (or an equivalent ionic-contamination process-control check) is what confirms ongoing production stays within the qualified envelope.

Practical Examples

A contract manufacturer switching to a new no-clean flux paste for a customer's board is a typical case for SIR qualification: rather than assuming the new flux's "no-clean" datasheet claim applies equally to this specific board's pad geometry, pitch, and reflow profile, the CM runs SIR test coupons through the actual process and confirms insulation resistance holds up under humidity bias before releasing the flux change to production, then relies on routine ROSE testing per lot afterward as an ongoing process-control check.

A product with a high-impedance analog front end, for example a photodiode transimpedance amplifier stage or a capacitive sensing input, is a case where ionic contamination matters even with a nominally "safe" no-clean flux, because the leakage-current failure mode that concerns high-impedance nodes can occur at contamination levels well below what would ever cause a visible dendrite short on ordinary digital traces. This is a case where washing the board, even with an otherwise-acceptable no-clean flux, is often the more conservative choice specifically for the sensitive section of the board.

Design Considerations

• Match the test method to the question actually being asked. ROSE testing is the right tool for routine process-control screening (did this batch come out within normal limits); SIR testing is the right tool for qualifying whether a specific flux, process, or no-clean decision is actually sound for this board's design and environment. Using only ROSE testing to justify a no-clean decision on a sensitive board substitutes a proxy measurement for the property that actually matters.
• Consider the interaction with conformal coating explicitly. Coating residue under a conformal coating layer can trap moisture against the board rather than letting it evaporate, which can make marginal ionic contamination a bigger reliability risk under coating than it would be on an uncoated board in the same environment. A board that's adequately clean uncoated isn't automatically adequately clean once coated; confirm the coating vendor's and IPC-CC-830's guidance on pre-coating cleanliness requirements.
• High-impedance and RF sections warrant a stricter cleanliness standard than the board's general acceptance class implies. IPC acceptance class governs overall workmanship, but a sensitive analog or RF section can justify washing even on an otherwise no-clean, Class 2 board, since the leakage-current failure mode scales with the node's own impedance, not with the board's general classification.
• Don't assume a no-clean flux is validated for a new board just because it was validated for a previous one. Pad geometry, pitch, solder mask, and reflow profile all affect how much residue actually remains after reflow and how accessible it is to moisture; a flux qualified via SIR testing on one board design isn't automatically qualified for a meaningfully different one without re-testing.
• Ionic contamination and process qualification: qualifying a flux or no-clean process, and deciding whether washing is warranted for a specific design's sensitive nodes, is exactly the kind of manufacturing process decision Zeus Design's PCB design team supports as part of design-for-manufacture review.

Common Mistakes

• Treating "no-clean" as a guarantee rather than a claim that needs verifying for the specific board and process. The flux datasheet's no-clean claim is based on the manufacturer's own test conditions, which may not match a specific board's pad geometry, reflow profile, or operating environment closely enough to apply without qualification.
• Relying on a visual inspection to judge cleanliness. Ionic residue that causes electrochemical migration or leakage current is often not visible at all, particularly light no-clean flux residue; a board that looks clean can still carry enough contamination to fail in the field under humidity and bias.
• Skipping SIR qualification on a flux or process change because ROSE testing "passed." ROSE testing measures bulk ionic contamination, not the insulation-resistance behaviour under humidity and bias that actually predicts field reliability; passing a ROSE check doesn't establish that a new flux or process is safe for a sensitive design.
• Applying conformal coating over a board's cleanliness assumptions from an uncoated design, without re-evaluating whether trapped residue under the coating changes the moisture-exposure risk for that same level of contamination.