How Should You Lay Out the RF Section of a PCB?

Detailed Explanation

RF layout is one area of PCB design where violating the rules produces immediate, measurable consequences: reduced radio range, failed regulatory emissions testing, or both. The good news is that the rules are consistent across protocols — the same principles apply whether you are routing a 2.4 GHz BLE module, a 915 MHz LoRa transceiver, or a 5 GHz Wi-Fi chip.

This guide covers the five areas that govern RF PCB layout in order of importance.

For background on why frequency matters for antenna sizing and PCB layout, see what are RF signals and how are they used in electronics?.

1. The 50Ω RF Trace

Every path that carries RF energy — from the radio IC's antenna pin to the antenna feed — must be a controlled-impedance 50Ω transmission line. This is almost universally implemented as a microstrip (a trace on the outer copper layer with a solid reference plane beneath it) or a coplanar waveguide with ground (CPWG) (a trace flanked by ground copper on the same layer, with a reference plane below).

The required trace width depends on three stack-up parameters: the dielectric material's relative permittivity (εᵣ), the dielectric height between the trace and the reference plane, and the copper thickness. For a typical 2-layer FR4 board with 1.6 mm total thickness and 1 oz copper:

• The top-layer microstrip trace for 50Ω is approximately 2.8–3.0 mm wide (εᵣ ≈ 4.4, 0.74 mm dielectric to inner copper).
• On a 4-layer board with a layer 1–layer 2 prepreg of 0.2 mm (a common stack-up), the same 50Ω microstrip is approximately 0.35–0.45 mm wide.

Use your EDA tool's built-in transmission-line calculator or a dedicated tool like Saturn PCB Design Toolkit, feeding it your fab house's actual material data — not generic textbook εᵣ values. See what is controlled impedance PCB design? for how the calculation works.

Key routing rules for the RF trace:

• Keep it as short as practically possible. At 2.4 GHz, a quarter-wavelength is 31 mm — a long RF trace is itself an antenna, radiating energy you meant to deliver to the real antenna.
• No right-angle bends. Use 45° chamfered corners or curved bends. A right-angle bend changes the effective trace width at the corner, creating a small impedance discontinuity.
• No vias on the RF trace unless the reference plane transitions with it. Each via introduces a small capacitive discontinuity; its impact grows with frequency. Where a layer change is unavoidable, model the via as a parasitic element and compensate in the matching network.
• No parallel signal traces alongside the RF trace. Other traces coupling into the RF path act as parasitic capacitance, shifting the impedance.

2. The Ground Plane Under the RF Section

The ground plane directly beneath the RF trace is the return current path for the RF signal and one of the two conductors that defines the microstrip transmission line's impedance. It must be solid copper — no cuts, slots, gaps, or traces — in the area under and around the RF trace.

This extends to the full area of the RF section, not just the trace itself:

• No signal traces routed through the ground plane layer under the radio IC or RF trace.
• No power plane splits under the RF section. If a power plane occupies the reference layer, it must be continuous under the RF trace.
• Stitching vias between ground planes on different layers should surround the RF trace at spacing less than λ/10 (less than 12.5 mm at 2.4 GHz) to suppress surface-wave modes. This is especially important on multilayer boards where ground continuity between layers matters.

For a full treatment of PCB power and ground plane design principles, see how do you design PCB power and ground plane layouts?.

3. The Antenna Keepout Zone

Any antenna — chip antenna, PCB trace antenna, whip antenna stub — requires a copper-free zone around and beneath it. The keepout dimensions are defined in the antenna's datasheet and are non-negotiable: placing copper within the keepout shifts the antenna's resonant frequency, reduces radiation efficiency, and alters its impedance from the 50Ω design point.

Key keepout rules:

• No ground copper within the specified keepout on any layer. This includes the ground plane on inner layers, not just the top copper.
• No signal traces, vias, or component pads within the keepout area.
• Keep metallic enclosure walls at the specified minimum distance from the antenna. A grounded metal enclosure wall that's too close acts like a partial shield, reflecting RF energy back toward the board.
• Board edge under the antenna should have no metallic edge plating. On boards with edge-castellation for module mounting, ensure the RF antenna area does not overlap a castellated zone.

For pre-certified modules (ESP32-S3-MINI, nRF52840, SX1262 in module form), the module's mechanical drawings and integration guide define the keepout. The host PCB must honour these exactly — the module's FCC/CE/ACMA certification was obtained with those keepout dimensions in place.

4. Impedance Matching Network Placement

Between the radio IC's RF output and the antenna, most designs require a discrete π or T matching network (two to three capacitors and inductors, typically 0402 or 0201 footprint) to transform the IC's RF output impedance to 50Ω. The component values come from the IC's reference design — do not substitute "similar" values without RF simulation.

Placement rules for the matching network:

• Place the matching network as close to the IC's RF pin as possible — ideally within 2–3 mm of the RF pad.
• Pads and traces within the matching network must also be 50Ω geometry or kept to stub lengths short enough (< λ/20 at the operating frequency) that their impedance deviation is negligible.
• Leave pads for all network components populated with 0Ω shorts on unused positions to allow tuning during production. RF layout almost always needs some adjustment on the first boards.

For an IC-specific example of matching network design, crystal selection, and power supply layout for a LoRa transceiver, see how do you design the hardware around an SX1262 or SX1276?.

5. Radio IC Supply Decoupling

Radio ICs are far more sensitive to power supply noise than digital logic. The datasheet specifies one or more decoupling capacitor positions for the RF supply pin — these must be placed as close to the pin as possible and connected with the shortest possible trace before reaching the via to the ground plane.

A typical RF supply decoupling scheme uses two capacitors in parallel: a 100 nF ceramic (for mid-frequency noise) and a 10–100 pF ceramic (for GHz-range supply noise), both in 0402 footprint, both with traces shorter than 1 mm to the supply pin and direct vias to a solid ground plane.

Do not route the RF supply through a thin trace shared with digital circuitry. Use a ferrite bead or a small inductor (e.g. 100 nH at the operating frequency) to isolate the RF supply from the rest of the digital power rail.

For designs combining a custom PCB with a pre-certified radio module, Zeus Design's PCB layout team covers impedance matching, keepout compliance, ground plane integrity, and pre-submission radiated emissions pre-testing — get in touch with Zeus Design to discuss RF layout review.

Design Considerations

• Validate impedance with test coupons: for any RF PCB where the RF section is non-trivial (board-level antenna design, multi-band, or mixed-signal with tight SNR requirements), request impedance test coupons from the fab house on the first production run. Calculation gets you close; a test coupon confirms the as-built result.
• Crystal placement: every radio transceiver requires an accurate, stable frequency reference crystal. The crystal should be placed as close to the IC as possible, with a guard ring of stitching vias between the crystal traces and other signals, and a local ground plane solid in the crystal's footprint area. The load capacitance values specified in the IC datasheet are not interchangeable with nearby available values.
• Via stitching at board edges and near the RF section: a ring of ground stitching vias around the RF section suppresses parasitic surface currents that can couple RF energy into other parts of the board and cause unexpected emissions.
• Verify layout with a pre-compliance scan before final production: a pre-compliance radiated emissions scan on the first PCB prototype (many electronics test labs offer this as a quick informal service) identifies layout-related emissions problems before the full, expensive certification test. A layout fix costs little at prototype stage; a re-spin after certification failure is expensive.

Common Mistakes

• Routing the RF trace at an arbitrary width: many engineers treat the RF trace like a normal signal trace and route it at the default track width. At 2.4 GHz on a typical 2-layer board, the default 0.25 mm trace is nowhere near 50Ω (it presents approximately 100–130Ω) — this creates a significant reflection and reduces transmitted power.
• Placing copper under the chip antenna "just to fill space": copper fills placed for thermal or aesthetic reasons on the back of the board under a chip antenna de-tune it. This is the single most common cause of range and sensitivity failures on first-spin boards using certified BLE or Wi-Fi modules.
• Assuming the module is certified so layout doesn't matter: pre-certified modules are certified as a stand-alone unit on a reference host board with specific keepout and ground plane conditions. The host PCB must meet those conditions — the module's certification does not extend to the complete product automatically. A layout that violates keepout or ground plane requirements can cause the product to fail EMC testing despite a certified radio module.
• Skipping the matching network or substituting values without RF simulation: the matching network component values in the IC's reference design are determined by RF simulation and measured RF performance. Substituting "equivalent" values that are physically available but slightly different shifts the matching and can cost 2–4 dB of radiated power.
• Not budgeting for layout iteration: RF layout on the first board spin almost always requires some adjustment. Plan for at least one layout iteration on a new radio design — leave pads populated with shorts on matching network component positions to enable tuning.