How Do You Design the Hardware Around an SX1262 or SX1276?

Detailed Explanation

For LoRa modulation concepts, spreading factors, LoRaWAN architecture, and AU915 frequency planning, see What Is LoRa and LoRaWAN?. For configuring AU915 firmware and registering a device on The Things Network, see Connecting a LoRaWAN Device to The Things Network in Australia. This guide focuses on the hardware design: the schematic and PCB layout for a discrete SX1262 or SX1276 LoRa transceiver IC.

SX1262 vs SX1276: Which Should You Use?

The SX1276 was Semtech's dominant LoRa transceiver for most of the 2010s. The SX1262 is the current-generation replacement and is the correct choice for any new PCB design. The key hardware differences:

The most significant hardware difference is the external T/R switch required by the SX1276. This switch — a low-insertion-loss SPDT RF switch such as the PE4259 (Peregrine Semiconductor) or AS179 (Skyworks), rated for +20 dBm at 900 MHz — adds BOM cost, a component placement constraint, and a potential reliability concern. The SX1262 eliminates this entirely.

The SX1276 remains in use inside existing pre-certified modules (Murata CMWX1ZZABZ, HopeRF RFM95W, AI-Thinker Ra-02). If you are designing a host board for one of these modules, the module's integration guide specifies the keepout and interface requirements — the RF design is handled inside the module.

SX1262 Pin Architecture

Understanding the SX1262 pin groupings is the starting point for schematic design.

Power pins:

• VBAT — main supply input, 1.8–3.7 V. All internal regulators derive from this rail.
• VDD_IO — I/O supply input, sets the logic voltage level for the SPI interface and DIO pins. Connect to the MCU's I/O supply: 1.8 V or 3.3 V depending on your MCU family. VDD_IO does not need to match VBAT.
• DCC_SW — DC-DC converter switch node. Connect to VBAT through an external inductor (typically 47 nH per Semtech reference design AN1200.32) when using DC-DC mode for better efficiency in TX. Omit the inductor and configure LDO mode in firmware for a simpler, fewer-component design.

SPI interface:

• NSS, MOSI, MISO, SCK — standard SPI bus, operating at VDD_IO logic levels. The SX1262 SPI supports clock speeds up to 16 MHz.

Control pins:

• BUSY — output; high while the IC is processing a command. The host MCU must wait for BUSY to return low before issuing the next SPI command. This is a hard requirement — not polling BUSY produces intermittent failures that are difficult to reproduce.
• RESET_N — active-low reset. Hold low for at least 100 µs at power-up or when re-initialising the radio.
• DIO1 — configurable interrupt output; typically assigned to TxDone, RxDone, or CadDone events in firmware.
• DIO2 — configurable; can be set in firmware to output TXEN/RXEN signals for an external FEM. Leave unconnected for a basic design without an external PA or LNA.
• DIO3 — configurable; can be set to supply regulated DC power to an external TCXO from the IC's internal regulator, enabling precise clock control without a separate TCXO supply circuit.

RF pin:

• RF_IO — single 50 Ω RF port. The integrated T/R switch routes this to the internal PA during transmit and to the LNA during receive.

Power Supply Design

VBAT Decoupling

Place the following capacitors as close as possible to the VBAT pin — within 1–2 mm — with direct vias to the ground plane:

• 100 nF ceramic, 0402, X5R or C0G — bypasses high-frequency switching noise.
• 10 µF ceramic, 0805, X5R — supplies the peak current during TX bursts. At +22 dBm, the SX1262 draws approximately 87 mA from VBAT; the 100 nF capacitor cannot supply this alone.

Where the radio IC shares a power rail with digital logic, route VBAT through a ferrite bead (e.g. 600 Ω at 100 MHz, 0402) to isolate it from digital switching noise.

DC-DC vs LDO Mode

The SX1262's internal power architecture supports a switchable DC-DC converter. In DC-DC mode, an external inductor on DCC_SW feeds a switching regulator that reduces the radio's supply current in TX by approximately 20–30% compared to LDO mode — a meaningful saving for duty-cycled sensors on a coin cell or small LiPo.

To use DC-DC mode: connect an external inductor between DCC_SW and VBAT (Semtech AN1200.32 specifies the inductance value and current rating), then call SetRegulatorMode(USE_DCDC) in your firmware startup sequence.

For LDO mode: omit the inductor, leave DCC_SW unconnected (the IC defaults to LDO on reset), and call SetRegulatorMode(USE_LDO). One fewer component but slightly higher TX current.

VDD_IO Supply

Decouple VDD_IO with 100 nF close to the pin. Ensure it matches your MCU's I/O voltage — connecting a 3.3 V MCU to an SX1262 with VDD_IO = 1.8 V drives SPI inputs above VDD_IO and risks damage.

32 MHz Crystal Selection and Load Capacitor Design

Both the SX1262 and SX1276 require a 32.000 MHz external crystal (or TCXO) as their frequency reference.

Crystal Specification Requirements

Common 32 MHz crystals specified in LoRa reference designs include the Abracon ABM8G-32.000MHZ-8-D2Y-T (3.2 × 2.5 mm, 8 pF CL, ±10 ppm) and Murata XRCGB32M000FXQ50Q0 (2.0 × 1.6 mm, 9 pF CL, ±10 ppm). Always verify the crystal specification matches your chosen IC's oscillator requirements — see how to select a crystal oscillator for an embedded system for the full specification framework.

Load Capacitor Calculation

The Pierce oscillator used in both the SX1262 and SX1276 requires two external capacitors — one on each crystal pin (XOSC_IN/XOSC_OUT) to ground. These must present the crystal's specified load capacitance (CL):

CL1 = CL2 = 2 × (CL_crystal − C_stray)

Where C_stray is the total parasitic capacitance of the oscillator traces and IC input pins — typically 1–3 pF for a compact layout where the crystal is placed within 3 mm of the IC.

Example — 10 pF crystal, 2 pF total stray:

CL1 = CL2 = 2 × (10 − 2) = 16 pF

Use NP0/C0G capacitors only — not X5R or X7R, whose capacitance varies significantly with temperature and voltage, shifting the crystal's effective load and therefore its frequency. Place both load capacitors within 1–2 mm of the crystal pins, with traces going directly to a ground via — not shared with other components.

Surround the crystal and load capacitors with a guard ring of ground stitching vias to reduce coupling from adjacent digital signal lines.

TCXO Option (SX1262 Only)

For designs operating across a wide temperature range (below −10°C or above 70°C), or where the radio must be ready quickly after waking from deep sleep, replace the passive crystal with a 32 MHz TCXO. Connect the TCXO output to XOSC_IN and leave XOSC_OUT floating. Configure DIO3 as the TCXO supply voltage output in firmware — the SX1262 will then power the TCXO only when the radio is active, keeping sleep current low.

A TCXO typically provides ±0.5–1 ppm stability over its rated temperature range, compared to ±20–50 ppm for a standard AT-cut crystal across the same range.

RF Matching Network and Antenna Trace

SX1262 Impedance Matching

The SX1262 RF_IO pin requires an impedance-matching circuit between the IC's internal PA/LNA and the 50 Ω antenna port. The typical configuration is a π-network: a shunt element to ground at the RF_IO side, a series element, and a shunt element to ground at the antenna side. All matching network components should be 0402 RF-grade parts with tight tolerance (±1–2% capacitors, ±1–5% inductors).

Semtech application note AN1200.32 (available on the SX1261/SX1262 product page) provides reference schematic values for each frequency band including 915 MHz (AU915/US915). Use those values as the starting point. Do not substitute values from a different frequency band or IC family without RF simulation — component values are specific to both the target frequency and the IC's output impedance.

Leave one or two extra 0402 pads populated with 0 Ω shorts on the board for matching network positions — RF circuits almost always require one iteration of component value tuning on first prototypes.

50 Ω RF Trace Routing

From the matching network output to the antenna feed (SMA connector or chip antenna pad), the PCB trace must be a 50 Ω controlled-impedance microstrip or coplanar waveguide with ground (CPWG). On a typical 2-layer, 1.6 mm FR4 board:

• Microstrip (trace on top copper, solid ground plane on bottom): approximately 2.8–3.0 mm wide. Use your EDA tool's transmission-line calculator with your fab's actual dielectric constant — do not use generic εᵣ = 4.4 as a universal value.
• CPWG (trace flanked by ground copper on the same layer, solid reference plane below): narrower trace, better isolation from adjacent circuitry.

Routing constraints:

• No right-angle bends — use 45° chamfered corners or curves
• No vias on the RF trace
• No parallel signal traces running alongside the RF trace
• Keep it as short as possible — at 915 MHz, a quarter-wavelength is approximately 82 mm; even a 10–15 mm unterminated stub produces measurable reflections if not impedance-controlled

For the full treatment of 50 Ω trace calculations, ground plane design, antenna keepout zones, and stitching via placement, see how should you lay out the RF section of a PCB?.

SX1276 External T/R Switch

The SX1276 exposes separate RFO_HF (TX output, >600 MHz band) and RFI_HF (RX input) pins. These must be combined to a single antenna port via an external SPDT RF switch. Choose a switch rated for +20 dBm input power at 900 MHz, with insertion loss below 0.5 dB and isolation above 20 dB — commonly specified parts include the PE4259 (Peregrine Semiconductor) and AS179 (Skyworks).

The TX path routes from PA_BOOST through the TX matching network to one switch port; the RX path routes from the other switch port through the RX LNA matching network to RFI_HF. DIO2 on the SX1276, configured by the protocol stack as an RF switch control output, drives the switch select pin.

Pre-Certified Module Alternative

Designing around a bare SX1262 is appropriate when:

• You need direct firmware access to all radio parameters (LoRa CAD, proprietary protocols, advanced power management)
• Volume is high enough that BOM cost savings justify the RF design and certification effort
• You want the tightest possible control over the sleep/wake power profile

For most LoRaWAN product teams — especially those building their first radio product — pre-certified modules are the better choice. The module manufacturer has already produced the RF schematic, PCB layout, and regulatory certification. You connect via UART or SPI AT commands and follow the module's integration guide, which specifies the host PCB keepout zone (copper-free area surrounding the module's antenna section). This keepout is a condition of the module's pre-certification — violating it can invalidate the certification and require re-testing of the complete product.

For LoRaWAN products requiring custom SX1262 hardware design, RF trace layout, or ACMA certification planning, Zeus Design's PCB design team covers the complete radio hardware stack — discuss your LoRa hardware project with the team.

Design Considerations

• BUSY pin management: the BUSY pin must be low before the MCU sends any SPI command to the SX1262. A fixed delay (delay_ms(10)) is not a substitute — it works in the lab but fails under firmware timing changes, temperature extremes, or different radio states. Implement BUSY polling with a timeout in your SPI HAL from the start.
• Antenna selection for AU915: at 915 MHz, a λ/4 wire antenna is approximately 82 mm long. PCB trace antennas are feasible but require careful layout and copper keepout compliance. For a first board, an SMA connector paired with an external 900 MHz whip antenna provides a known 50 Ω load and isolates RF performance from PCB layout variables during bring-up.
• DC-DC inductor placement: the DCC_SW switching node generates RF noise at the DC-DC switching frequency. Place the external inductor as close to DCC_SW as possible, keep the DCC_SW trace short, and route it away from the crystal and RF trace.
• First-board RF verification: before closing the enclosure, measure the RF output power with a spectrum analyser or power meter at the antenna port. Verify both the output level (typically +14 dBm for LoRaWAN Class A) and the frequency (+/−200 kHz from the nominal channel centre frequency). A mismatched or open RF trace shows as dramatically reduced output power.
• Host PCB keepout for pre-certified modules: the module keepout dimensions are a certification condition, not a guideline. Common violations are copper pours on inner layers under the antenna section and SMA connectors placed too close to the antenna edge. Follow the module's integration guide dimensions exactly.

Common Mistakes

• RF trace at the default track width: routing the RF trace from the matching network to the antenna at the EDA tool's default width (typically 0.1–0.25 mm) produces a trace impedance of approximately 100–150 Ω at 915 MHz on a standard 2-layer FR4 board — a severe mismatch that reflects power back into the IC and can reduce usable output by 3–6 dB. Calculate the correct width using the actual board stack-up parameters.
• Crystal load capacitors placed too far from the IC: capacitors placed more than 5 mm from the crystal pins accumulate parasitic trace inductance and stray capacitance that shift the effective load, pulling the oscillation frequency away from 32.000 MHz. Semtech's reference designs place the load capacitors within 1–2 mm of the crystal pins — follow this closely.
• Mismatching VDD_IO to the MCU I/O voltage: the SX1262 SPI pins and DIOs operate at VDD_IO level. Driving them from a 3.3 V MCU when VDD_IO = 1.8 V exceeds the absolute maximum on the SX1262's inputs. Match VDD_IO to the MCU's I/O supply, or use a level shifter if they differ.
• Not polling BUSY before SPI commands: BUSY going high signals that the SX1262 is executing an operation. Sending the next command before BUSY returns low corrupts the register state. This failure mode is intermittent — it appears only when commands are issued faster than the IC can process them — and is difficult to catch without logic analyser capture or explicit BUSY monitoring.
• Using LDO mode in a battery-powered design: LDO mode requires no external inductor, which simplifies the BOM. However, at +14 dBm TX the efficiency penalty compared to DC-DC mode is significant for small battery applications. Add the DC-DC inductor on DCC_SW (per AN1200.32) from the first prototype — it is much harder to add to a finished PCB layout than to include it at the start.