How Do You Verify PCB Trace Impedance with a TDR?

Detailed Explanation

Signal integrity design work — controlled impedance stack-up specification, trace width calculation, termination selection — all happens before the board exists, based on a field solver or impedance calculator's prediction of what a given geometry and dielectric will produce. Time-domain reflectometry (TDR) is the measurement technique that closes the loop: it verifies what a fabricated board actually delivers, on the physical board itself, rather than trusting the calculation alone.

How TDR Works

A TDR instrument launches a very fast voltage step (rise times in the tens of picoseconds for high-end instruments, allowing fine spatial resolution) into the trace under test and continuously monitors the voltage at the launch point. As long as the trace's impedance stays constant, the step propagates without producing any reflection back toward the source. At any point where the impedance changes — a via, a connector, a width change, a stub, or the bulk trace impedance itself drifting from its target — part of the incident wave reflects back, and the TDR measures both the size and the polarity of that reflection at the launch point.

Because the reflected step takes a known round-trip time to return (set by the trace's propagation velocity, the same velocity used in signal-integrity propagation-delay calculations), the TDR converts elapsed time into physical distance along the trace, and displays the result as impedance versus position — not simply "the trace failed a test," but exactly where along its length the deviation occurs.

Reading a TDR Trace

A TDR plot shows impedance on the vertical axis against distance (converted from time) on the horizontal axis:

• A flat trace at the target impedance (for example, a flat line at 50Ω for a single-ended trace, or 90Ω/100Ω for a differential pair) indicates a well-controlled, matched line with no significant discontinuities.
• A step up in impedance (the trace briefly reads higher than the surrounding baseline) typically indicates an inductive discontinuity — a narrow trace section, a via with excess inductance, or a connector pin with more series inductance than the surrounding line.
• A step down in impedance (the trace briefly reads lower than the surrounding baseline) typically indicates a capacitive discontinuity — a wider trace pad, a via stub, or a connector footprint with excess capacitance to a nearby plane.
• An open circuit (an unterminated trace end) shows as a large positive-going reflection, and a short circuit shows as a large negative-going reflection — the same reflection-coefficient behaviour described in signal integrity basics, just observed directly on the physical board rather than calculated.

Spatial Resolution and Rise Time

A TDR's ability to distinguish two closely-spaced discontinuities — for example, a via immediately followed by a connector pad — depends directly on the step generator's rise time: a faster rise time resolves finer spatial detail, while a slower step edge blurs together discontinuities that are close together into a single, harder-to-interpret feature. This is why dedicated TDR instruments used for high-speed digital validation (DDR routing, SerDes channels) specify rise times in the tens of picoseconds, while a general-purpose oscilloscope with an add-on TDR step module — adequate for a rough check — has correspondingly coarser resolution.

TDR vs VNA

TDR and a vector network analyser (VNA) measure the same underlying reflection phenomenon in different domains. A TDR operates in the time domain, launching a step and observing reflections over time — the natural tool for locating exactly where along a trace or cable a discontinuity occurs. A VNA operates in the frequency domain, sweeping a range of frequencies and measuring return loss (S11) at each one — the natural tool for confirming an impedance match across a specific operating band, as used in RF impedance matching network design. Many modern VNAs can compute an equivalent time-domain view via an inverse Fourier transform of swept frequency-domain data, which is a common way high-end VNAs also perform fault-location work — but a dedicated TDR remains the simpler, more direct tool specifically for verifying PCB trace impedance by position along the trace.

Calibration and Test Fixture Design

A TDR measurement is only as accurate as its calibration and its connection to the board under test. Standard practice is an open/short/load calibration at the reference plane — the point where the measurement is meant to begin — so that the instrument's own cabling and connectors are mathematically removed from the result rather than appearing as a false discontinuity at the very start of the trace. The physical launch point onto the board matters just as much: a well-designed test coupon includes a controlled-impedance launch structure (commonly an SMA edge-launch connector transitioning cleanly into the trace geometry under test) rather than a bare, uncontrolled via or probe touchdown, which would itself introduce a discontinuity that's difficult to distinguish from a genuine fabrication defect further down the trace.

Practical Examples

A high-speed digital board's first article inspection includes TDR measurement of a dedicated test coupon fabricated alongside the production panel, using the same stack-up and trace geometry as a critical DDR or SerDes net, confirming the panel's actual impedance matches the design target before the full production run proceeds.

Locating an intermittent connector fault on a cable assembly or board-to-board interconnect uses TDR to pinpoint the exact distance to a suspect connector or crimp, rather than visually inspecting the entire cable run — the reflection's round-trip time converts directly to a distance from the TDR's launch point.

Design Considerations

• Include a dedicated TDR test coupon on the fabrication panel for critical high-speed nets, using the same stack-up and trace geometry as the actual signal, rather than attempting to probe the production trace itself and risk damaging or loading it.
• Design a proper controlled-impedance launch structure into any test point meant for TDR or VNA measurement. An uncontrolled bare via or ad hoc probe touchdown introduces its own discontinuity that can be difficult to separate from a genuine fabrication issue on the trace being measured.
• Match the TDR's rise time (and therefore spatial resolution) to the discontinuity spacing that actually matters for the design. A coarse-resolution measurement is adequate for confirming bulk trace impedance but will not resolve closely-spaced via/pad transitions on a dense high-speed layout.
• Always calibrate before measuring, and repeat calibration if cables or fixtures change. An uncalibrated measurement folds the test setup's own impedance discontinuities into the result, producing a trace that looks like a fabrication defect when the actual cause is the measurement path itself. Zeus Design's PCB design team specifies controlled-impedance stack-ups and works with fabricators on first-article TDR verification for high-speed digital and RF boards.

Common Mistakes

• Skipping calibration and trusting the raw measurement. Without an open/short/load calibration at the intended reference plane, cable and connector discontinuities in the test setup itself appear indistinguishable from genuine discontinuities on the board.
• Probing a production trace directly with an uncontrolled test point rather than including a proper launch structure on a dedicated test coupon, introducing a measurement-induced discontinuity that muddies the result right at the point where the measurement begins.
• Assuming a TDR discrepancy against the field-solver prediction is automatically a fabrication defect, without first checking measurement calibration and the actual as-built dielectric thickness — see the FAQ above for the more likely causes to rule out first.
• Using a step generator or scope with insufficient rise time for the discontinuity spacing being investigated, then misreading two closely-spaced features as a single, larger one because the measurement's spatial resolution couldn't separate them.
• Treating TDR and VNA measurements as interchangeable without considering which domain actually answers the question being asked — a discontinuity's physical location is a TDR question; an impedance match's behaviour across an operating frequency band is a VNA question.