Signal Integrity in PCB Design: Reflections, Crosstalk, and Termination

Detailed Explanation

Every PCB trace is a physical structure with distributed inductance, capacitance, and resistance. At low frequencies and slow signal transitions, these parasitics are small enough to ignore — the trace looks like a simple conductor. At high frequencies or fast edge rates, these parasitics determine how signals travel, whether they reflect, and whether adjacent signals interfere. This is the domain of signal integrity.

Understanding signal integrity is not limited to RF or GHz-speed designs. Modern LVCMOS GPIO, USB, Ethernet, HDMI, DDR memory, and FPGA I/O all produce edge rates fast enough to make SI considerations relevant on nearly every professional PCB.

When Does a Trace Become a Transmission Line?

The key criterion is not the signal frequency — it is the signal's rise time (the time to transition from 10% to 90% of the final amplitude) relative to the trace's propagation delay.

A trace behaves as a lumped element (a simple conductor) when its one-way propagation delay is much less than the signal's rise time. As propagation delay approaches a significant fraction of the rise time, the trace must be treated as a transmission line with a characteristic impedance.

The commonly used rule of thumb: treat a trace as a transmission line when:

T_propagation > T_rise / 6

where T_rise is the signal's 10%–90% rise time and T_propagation is the trace's one-way propagation delay.

Propagation delay on a PCB trace depends on the dielectric constant of the surrounding material. Typical values for FR4:

• Microstrip (trace on outer layer, one-sided dielectric exposure): typically 140–170 ps/inch (55–67 ps/cm)
• Stripline (trace buried between two planes, full dielectric immersion): typically 170–200 ps/inch (67–79 ps/cm)

Applying the criterion:

This table illustrates why signal integrity has become important for mainstream embedded PCBs: modern MCU and FPGA outputs have rise times well under 1 ns, making 1–2 cm traces electrically significant.

Characteristic Impedance and Why It Matters

A transmission line has a characteristic impedance Z₀ — the ratio of voltage to current for a wave travelling along the line. For a microstrip trace:

Z₀ is set by the trace width, copper thickness, dielectric height, and dielectric constant of the PCB material. On FR4 with ε_r ≈ 4.2 (a typical effective value for microstrip — the true value varies with the specific laminate), a single-ended 50Ω microstrip trace on a 4-layer board with a 0.2 mm dielectric to the adjacent plane is typically around 0.35–0.40 mm wide; a 90Ω differential pair is typically routed as two traces each approximately 0.15 mm wide with 0.15 mm gap. These are starting estimates — the actual geometry depends on the specific stack-up and must be confirmed with an impedance calculator or the PCB fabricator.

The significance of characteristic impedance: a signal wave travelling down a transmission line continues undisturbed only as long as the impedance stays constant. Any change in impedance — trace width change, via, connector pin, or IC input pad — causes a portion of the signal energy to reflect back toward the source.

Reflections

The fraction of signal energy reflected at an impedance discontinuity is determined by the reflection coefficient:

Γ = (Z_L − Z₀) / (Z_L + Z₀)

Where Z_L is the impedance of the load (or the impedance after the discontinuity) and Z₀ is the characteristic impedance of the trace.

Key cases:

An unterminated CMOS receiver input is nearly an open circuit — nearly the entire incident wave reflects. The reflected wave then travels back to the source, where the driver's output impedance determines how much of it reflects again. This bouncing creates ringing: oscillations on the waveform that can cause a receiver to trigger multiple times on a single edge, violating setup and hold time requirements or corrupting data.

On an oscilloscope, reflections appear as overshoot, undershoot, and ringing in the first nanoseconds after a transition. At the system level, they cause communication failures, bit errors, and intermittent lock-up that is extremely difficult to reproduce.

Termination Strategies

Termination matches the line impedance to eliminate or absorb reflections.

Source Termination (Series Resistor)

A resistor R_s placed in series with the driver output makes the effective source impedance equal to Z₀:

R_s = Z₀ − R_driver

where R_driver is the driver IC's output impedance (typically 10–30Ω for CMOS; check the datasheet — output impedance is often listed as V_OH/I_OH or in SI simulation models).

The signal launches from the driver as a half-amplitude wave (the source and line form a voltage divider), travels to the unterminated receiver, reflects with Γ = +1 (doubling to full amplitude), then returns to the source. Because the source impedance is now matched to the line, this return wave is fully absorbed and no further reflections occur.

Source termination:

• Adds only one resistor per signal — efficient for point-to-point links
• Creates a slow-rising half-amplitude wave until the reflection returns (may be an issue for very short round-trip delays)
• Does not work cleanly with multi-drop (daisy-chain) topologies

Typical values: 22–47Ω series resistors are common starting points for 50Ω single-ended traces driven by CMOS with 10–30Ω output impedance.

End Termination (Shunt Resistor)

A resistor to GND (or to a mid-supply voltage for Thevenin termination) at the receiver equal to Z₀ absorbs the incoming wave at the load:

R_end = Z₀

The wave arrives at full amplitude and is absorbed by R_end. No reflection occurs. This is preferred for clock distribution (where the signal must arrive cleanly at a specific amplitude immediately, without waiting for a reflection round-trip) and for multi-drop buses.

The cost: R_end = 50Ω to GND draws 66 mA for a 3.3 V logic high signal — significant static power for a logic signal. Thevenin termination (a voltage divider from Vdd to GND with parallel combination equal to Z₀, midpoint at the logic threshold) reduces the static current compared to a simple pull-down.

AC Termination

An RC network (capacitor in series with resistor) to GND combines a DC-blocking capacitor with a termination resistor. At signal frequencies, the capacitor is transparent and the resistor terminates the line; at DC, the capacitor blocks current, eliminating the static power draw. Used where end termination is needed but DC power consumption is unacceptable.

Crosstalk

When two traces run in parallel, their electric and magnetic fields couple energy between them:

• Capacitive coupling (electric field): voltage transitions on the aggressor trace couple displacement current into the victim trace through mutual capacitance between the traces. The effect is proportional to the rate of voltage change (dV/dt) and the mutual capacitance.
• Inductive coupling (magnetic field): current changes in the aggressor induce a voltage in the victim trace through mutual inductance. The effect is proportional to the rate of current change (dI/dt) and the mutual inductance.

Crosstalk appears as:

• Near-end crosstalk (NEXT): interference at the source end of the victim trace
• Far-end crosstalk (FEXT): interference at the load end of the victim trace

The magnitude of crosstalk depends on:

1. Trace spacing — coupling falls off rapidly with distance. Doubling the spacing reduces capacitive and inductive coupling substantially.
2. Parallel run length — longer parallel runs accumulate more coupling.
3. Proximity to reference plane — a close reference plane reduces field coupling between adjacent traces by confining the fields.

The 3W rule (a widely used layout guideline, not a specification): maintain a minimum edge-to-edge spacing of twice the trace width (so the centre-to-centre spacing is three times the trace width) between adjacent signal traces. This is a rule of thumb that aims to limit mutual capacitance to roughly 20% of each trace's self-capacitance, reducing coupling to manageable levels. For critical high-speed pairs (clock traces, high-speed buses), more spacing or orthogonal routing on adjacent layers is typically required.

Reference Planes and Return Currents

Every signal has a return current — the current that flows from the receiver back to the source to complete the circuit. At high frequencies, return currents do not simply flow through the nearest available GND path; they flow in the reference plane directly beneath the signal trace, taking the path of least impedance (which at high frequencies is the path of least inductance — i.e. directly beneath the signal).

This has critical implications for PCB layout:

• Solid, unbroken reference planes are essential for signal integrity and EMC. A gap, slot, or cutout beneath a high-speed signal trace forces the return current to detour around the gap, increasing loop inductance, creating a current loop antenna that radiates, and degrading SI.
• Via transitions need return current paths. When a signal transitions from one layer to another through a via, its return current must also transition. Without a GND via or stitching capacitor nearby, the return current must travel a long distance through the plane layers, creating inductance and common-mode noise.
• Split planes and plane splits at signal crossings concentrate return current loops and degrade both SI and EMC. Avoid routing high-speed signals across plane splits. See PCB power and ground plane design for plane design principles.

Edge Rates and Bandwidth

A digital signal's spectral content extends to frequencies determined by its rise time, not its clock frequency. The knee frequency — the approximate bandwidth of a digital signal — is:

f_knee ≈ 0.35 / T_rise

A signal with a 1 ns rise time has significant spectral content up to approximately 350 MHz. A signal with a 100 ps rise time has content to 3.5 GHz. This is why:

• A 1 MHz square wave with a 1 ns rise time requires controlled impedance treatment at those rise-time frequencies, not at 1 MHz.
• EMC emissions from digital logic are determined by edge rates, not clock frequency — fast logic driving long traces radiates at frequencies far above the clock fundamental.

For a 50 MHz MCU GPIO switching at 3.3 V with a 2 ns rise time, the SI-relevant bandwidth is approximately 175 MHz, and any trace longer than approximately 0.5 inches should have attention paid to its impedance and termination.

Design Considerations

• Identify critical nets early — classify signals by their rise time and route length at the start of the PCB layout, not as an afterthought. A DDR data bus and a 50 MHz clock line need to be called out before placement so component positions minimise critical trace lengths.
• Consult the interface specification — USB 2.0, USB 3.x, Ethernet, HDMI, and most other standard interfaces specify their required trace impedance and matching tolerances. These are not optional design targets — they are compliance requirements.
• Impedance calculators before fabrication — use a PCB impedance calculator (built into most EDA tools, or available from fabricators as a web tool) to confirm that the stack-up and trace geometry produce the target impedance before the board is fabricated. Confirming impedance after the fact requires a TDR (time-domain reflectometer). See controlled impedance PCB design for how to specify and verify impedance.
• RF layout guidelines apply to high-speed digital — the layout guidance for RF signals (solid ground beneath signal, minimal vias, controlled spacing) applies equally to high-speed digital. See RF PCB layout guidelines for principles that transfer directly to high-speed digital routing.
• SI and EMC are coupled — poor signal integrity (uncontrolled impedance, return path breaks, unterminated traces) is also a significant source of conducted and radiated emissions. Improving SI generally improves EMC performance simultaneously. See how to reduce PCB EMI for EMC-specific layout considerations.

For high-speed PCB designs requiring formal signal integrity analysis — including impedance-controlled stack-ups, termination specification, and eye diagram simulation — Zeus Design's PCB design team designs high-speed digital boards for commercial embedded products.

Common Mistakes

• Treating all traces as lumped conductors — engineers often add termination resistors after layout as an afterthought, placing them far from the driver or at the wrong end of the trace. Series termination resistors must be placed within a millimetre or two of the driver output pin; end termination resistors at the receiver.
• Routing a high-speed signal across a plane split or cutout — the return current is forced to detour, creating a large current loop that radiates and degrades both SI and EMC. Never route a high-speed net across a power plane boundary.
• Ignoring via stub resonances in multilayer designs — a through-hole via on a 4-layer board creates a stub below the inner signal layer where the via continues to the bottom copper. At high frequencies (GHz range), these stubs resonate and cause absorption notches in the transmission. Back-drilling or back-drilled vias are used in high-performance designs to remove stubs.
• Using default trace width for all signals — PCB EDA tools route everything to the minimum manufacturing clearance unless told otherwise. High-speed signals need width specified to hit target impedance; this must be set as a routing constraint before layout begins, not corrected after.
• Ignoring differential pair skew — differential pairs (USB D+/D−, Ethernet TX+/TX−, LVDS) depend on the two traces arriving at the receiver simultaneously. Unequal trace lengths introduce skew that degrades the differential signal and can cause common-mode noise. Match lengths to within the tolerance specified by the interface standard (typically within 5–15 mils for most PCB-speed differential pairs).