How Do You Fan Out and Escape-Route a Fine-Pitch BGA?

Detailed Explanation

A BGA (Ball Grid Array) package presents every one of its connections as a solder ball on a grid under the package body — unlike a QFP or SOIC, there's no lead sticking out from the package edge that a trace can simply run to. Only the balls on the outer edge of the grid have a clear path to the surrounding board; every ball inside that perimeter is physically surrounded by other balls on all sides, and the only way to reach it is straight down, through the board, via a via placed at or immediately next to that specific ball. Fanout (or escape routing) is the process of giving every ball that via, so the signal reaches a layer where normal routing can take over — it's a distinct, earlier step from general board routing, and it has to happen first, because the fanout pattern determines how much (or how little) routing channel is left between vias for anything else that needs to cross under the package.

The standard fanout pattern is the dogbone: a short trace runs from the ball's own SMT pad outward to a via placed just clear of the ball grid, rather than putting the via directly in the pad. The pad-trace-via shape resembles a dog's bone, which is where the name comes from. This is the default because it keeps the via (and its annular ring) off the solder pad itself, avoiding the wicking and voiding risk a via directly under a solder joint can create during reflow — see via-in-pad for the alternative where the via genuinely does go inside the pad, and why that requires an added fill-and-cap fabrication step to be reflow-safe.

Practical Examples

A 1.0 mm pitch BGA (common on many microcontrollers and simpler ICs) is usually the easiest case: the pitch is generous enough that ordinary through-hole vias fit comfortably in a dogbone pattern on a standard trace/space capability, and even boards with only four or six layers can often escape the whole package without needing microvias or via-in-pad at all.

A 0.5 mm (or finer) pitch BGA — typical of a high pin-count FPGA, SoC, or DDR memory device — is a fundamentally different problem: at that pitch, there is often not enough physical space between adjacent balls to fit a standard-size through-hole via and its annular ring at all, which is exactly the scenario that drives the microvia and via-in-pad discussion in types of PCB vias. The layer count and stack-up itself are frequently set by this requirement before the rest of the board's routing is even considered — see what is a PCB stack-up? for how BGA escape routing drives the minimum layer count on a dense design.

Design Considerations

• Calculate routing channel capacity from the actual ball pitch and your fab's real trace/space capability, not from a number that worked on a previous project's different-pitch package — see the FAQ above for how this changes with pitch.
• Route the outermost 1–2 rows of balls directly where possible, saving via count and routing layers for the interior rows that have no alternative but to escape through a via.
• Plan via technology (through-hole, microvia, or via-in-pad) against the specific package's pitch before committing to a stack-up — a package pitch that's genuinely too fine for through-hole vias will force a stack-up and fabrication cost decision that needs to be made early, not discovered after layout has already started.
• Stagger interior vias where the pitch allows it, rather than placing every via on a strict rectangular grid — a staggered pattern can open up marginally more routing channel between vias on a tight-pitch package, though the achievable pattern is ultimately set by the ball grid itself.
• Verify escape routing against your fab's actual annular ring, minimum via size, and minimum trace/space capability before finalising the pattern, since a fanout that looks fine in the layout tool can be unmanufacturable if it assumes a tighter tolerance than the chosen fab can reliably produce.
• Fine-pitch BGA layout: escaping a dense, fine-pitch package correctly the first time avoids a costly stack-up or layer-count respin partway through a project — professional PCB layout services plan the fanout and via strategy against the fab's actual capability as part of the initial stack-up decision.

Common Mistakes

• Starting general board routing before the BGA fanout is fully planned, then discovering partway through that the escape pattern doesn't leave enough routing channel for the rest of the board's nets to pass underneath the package.
• Assuming a routing-channel width or via pattern that worked on a previous, coarser-pitch package will carry over to a finer-pitch one without recalculating against the new pitch and the fab's actual capability.
• Placing interior-row vias without first confirming the fab can actually manufacture a via and its annular ring at that pitch, discovering the conflict only when the design comes back from a manufacturability check or fails at the fab house.
• Treating dogbone vias and via-in-pad as interchangeable defaults rather than a deliberate choice driven by pitch — using via-in-pad everywhere adds unnecessary fill-and-cap fabrication cost on rows where a standard dogbone pattern would have fit comfortably.