What Is a PCB Stack-Up, and How Do You Design One?

Detailed Explanation

A stack-up defines the vertical structure of a PCB: how many copper layers it has, what each layer is assigned to (signal routing, a ground plane, a power plane), and the dielectric material and thickness separating them. It's decided early in the design process because it directly constrains routing, plane integrity, and, for any high-speed or RF signal, the impedance that routing can achieve.

Layer count is the most visible stack-up decision, but assignment matters just as much: a four-layer board with two routing layers sandwiching a solid ground plane and a power plane behaves very differently, electrically, than a four-layer board with all four layers used for signal routing and no dedicated plane at all. The former gives every signal a clean, low-impedance return path; the latter saves nothing on cost but loses most of the EMI and signal-integrity benefit layer count was meant to buy.

Choosing a Layer Count: 4 vs 6 vs 8+ Layers

Single vs double-sided vs multi-layer covers the broader category decision: when routing density or signal-integrity needs push a design past two layers. Once a design is in multi-layer territory, the next question is how many layers, and that's driven by routing channel count, plane requirements, and impedance-control needs rather than board size alone:

• 4 layers: the common default for a mixed digital/analog board, with two outer signal layers sandwiching a ground plane and a power plane. Enough routing channels for moderate component density, with every signal on either outer layer given a continuous, adjacent reference plane. Handles one or two controlled-impedance interfaces (USB, a single high-speed digital bus) without difficulty.
• 6 layers: typically added when a 4-layer stack-up runs out of routing channels before the design runs out of components, or when a design needs a dedicated reference plane closer to more of its signal layers than a 4-layer stack-up can provide (for example, separating a noisy digital ground from a quiet analog ground each with their own adjacent plane). A common 6-layer arrangement is signal / ground / signal / signal / power / signal, giving two of the four signal layers their own adjacent ground reference.
• 8+ layers: generally required once a design has a high pin-count BGA (an FPGA, SoC, or high-pin-count microcontroller) whose fan-out alone consumes several routing layers, multiple independent power domains that each need their own plane, or several simultaneous controlled-impedance interfaces each needing a tightly controlled dielectric height to its own reference plane. Layer count in this range is usually driven directly by BGA escape routing requirements: the component's pitch and ball count set a minimum layer count before the rest of the board is even considered.

These are common starting points, not fixed rules. The right count for a specific board depends on its actual routing density, plane, and impedance requirements, which is why layer count is decided alongside plane assignment rather than chosen from a lookup table.

Practical Examples

A common, well-proven four-layer stack-up for a mixed digital/analog board is: top signal layer, ground plane, power plane, bottom signal layer. This gives every signal on either outer layer a continuous, adjacent reference plane, which keeps return paths short and predictable, a major reason this configuration is a default starting point rather than something most designs need to deviate from.

A board with a high-speed differential pair (such as USB or a SerDes link) needs the stack-up decided before routing even starts, because the dielectric thickness between the signal layer and its reference plane is one of the variables that sets the controlled impedance of that trace. Changing the stack-up after routing means re-deriving every impedance-critical trace width from scratch. See signal integrity basics for how dielectric height and constant feed directly into that impedance calculation.

A board with a high pin-count FPGA might need 8 or more layers purely to escape-route the BGA's ball grid, well before routing density elsewhere on the board is even considered. In this case, layer count is effectively set by the largest component's footprint, not the overall design's complexity. See BGA fanout and escape routing for the dogbone pattern and routing-channel math behind that layer-count requirement.

Copper Weight Selection

Copper weight (thickness) is specified per layer, commonly in ounces per square foot: 0.5 oz (~17.5 µm), 1 oz (~35 µm), and 2 oz (~70 µm) are typical standard options, with outer and inner layers sometimes specified at different weights on the same board. Two things drive the choice:

• Current-carrying capacity. Thicker copper carries more current at the same temperature rise for a given trace width. See PCB trace width for current capacity for how copper weight and trace width combine to meet a current requirement.
• Achievable trace width and spacing. Thicker copper generally needs wider minimum trace width and spacing to fabricate reliably (the etching process removes copper from the sides of a trace as well as around it, so thicker copper etches less precisely at a given nominal width). A board with fine-pitch, high-density routing often specifies thinner copper specifically to hit tighter trace/space geometry, while a board carrying significant current on a few power traces may specify heavier copper on just those layers.

Standard weights and achievable minimum trace/space vary by fabricator process capability. Confirm both against your specific fab house before finalising a stack-up that depends on non-default copper weight.

Symmetric Stack-Up Construction

A stack-up should generally be built symmetric about its vertical centreline, mirroring copper weight and dielectric thickness above and below the middle of the board, to avoid warp. An asymmetric stack-up (heavier copper or thicker dielectric concentrated toward one side) expands and contracts unevenly as the board heats and cools during fabrication lamination and, later, reflow soldering, which can bow or twist the finished board enough to cause coplanarity problems with fine-pitch components.

This risk is directly related to the laminate's glass transition temperature (Tg). Standard FR4 typically has a Tg around 130–145°C, and reflow profile design notes that extended soak time above Tg on a thin or asymmetric board is a common cause of warp during reflow. A symmetric stack-up doesn't eliminate this risk entirely, but it balances the mechanical stress across the board's cross-section far better than an asymmetric one, and is standard practice for any stack-up beyond the simplest 2-layer board.

FR4 vs High-Speed Laminate

Standard FR4 (a glass-fibre-reinforced epoxy laminate, specified generically under IPC-4101) is the default dielectric material for the large majority of PCBs, and is adequate for most digital designs up to a few hundred MHz to low GHz. Its dielectric constant (Er) is commonly cited as approximately 4.2 for microstrip calculations, though the true value varies, commonly in the range of about 3.8 to 4.8, depending on the specific laminate grade, resin content, and signal frequency, which is why a fabricator's actual stack-up parameters should be used for any impedance-critical calculation rather than a generic default.

For higher-frequency RF work or very high-speed digital links (multi-gigabit SerDes, some high-speed differential pairs), standard FR4's dielectric loss (loss tangent) becomes a limiting factor: signal energy is absorbed by the material itself as frequency increases, attenuating the signal beyond what trace geometry alone can compensate for. High-speed laminates (such as those from Rogers or Isola) offer a lower and more frequency-stable Er and a substantially lower loss tangent than standard FR4, at a materially higher material cost. A common cost-control approach is a hybrid stack-up: high-speed laminate used only for the specific layers carrying RF or high-speed signals, with standard FR4 for the remaining layers, rather than specifying an entire board in the more expensive material.

Whether a design needs high-speed laminate at all depends on frequency and trace length, not board complexity alone. Confirm with your fabricator or an RF/signal-integrity engineer before assuming FR4 is (or isn't) adequate for a specific interface.

Design Considerations

• Decide plane assignment, not just layer count. A layer reserved for signal routing only helps if the adjacent layer actually provides a continuous reference plane for it.
• Loop in your fabrication house early. Dielectric thickness, copper weight, and even some material options vary by manufacturer, and the stack-up you specify has to be something they can actually build within tolerance.
• Account for impedance requirements before finalising dielectric thickness. If any net needs controlled impedance, the stack-up's dielectric height between signal and reference plane is a direct input to that calculation, not an afterthought.
• Don't over-spec layer count "to be safe". Every additional layer adds cost and lead time; a stack-up should match the design's actual routing density and plane needs, not an arbitrary safety margin.
• Stack-up coordination with fabrication: Getting an accurate, buildable stack-up requires close coordination with the intended fab house. Professional PCB design includes this fabrication-house alignment as a standard step before routing begins.

Common Mistakes

• Choosing layer count without assigning planes, ending up with the cost of a multi-layer board but little of its signal-integrity benefit.
• Finalising the stack-up after routing has already started, then discovering a controlled-impedance trace's width needs to change because the dielectric thickness wasn't fixed first.
• Assuming every fabrication house can build an identical stack-up. Copper weight and dielectric availability vary, and a stack-up specified without checking can come back with substitutions that change its electrical properties.
• Splitting a ground plane into multiple isolated islands "for noise separation" without understanding the return-path consequences. See our PCB power and ground plane design guide for when (and when not) to do this.
• Building an asymmetric stack-up (uneven copper weight or dielectric thickness across the board's centreline) without accounting for warp risk, then discovering fine-pitch components don't sit flat after reflow.