What Is PCB Routing, and How Do You Route a Board Well?

Detailed Explanation

Routing draws the actual copper that carries every signal defined in the netlist between the components placement has already positioned. It's constrained from multiple directions at once: the netlist dictates what must connect, the stack-up dictates which layers are available to route on, and the design rules dictate how: minimum trace width and spacing, via sizes, and any impedance targets for specific nets.

Routing isn't a single pass performed net by net in netlist order. It's worked in a deliberate sequence — most constrained nets first, most flexible nets last — because the nets with the least routing freedom need first claim on the board's cleanest, most direct paths, and every net routed changes what's still available to the ones that come after it.

Routing Priority: What to Route First, and Why

Routing power and ground through solid copper planes rather than discrete traces wherever the stack-up allows is standard practice for anything beyond the simplest two-layer board: a plane gives a far lower-impedance return path than a routed trace ever could, and it does so for every signal referenced to it at once rather than one net at a time. See PCB power and ground plane design for how plane assignment and pour strategy are decided.

Routing Techniques and Conventions

A handful of conventions show up on almost every well-routed board, independent of what the board actually does:

• 45-degree corners over 90-degree corners. A sharp right-angle bend leaves a small wedge of extra copper at the outside of the corner that etches less predictably than the trace on either side of it. Routing corners as two 45-degree bends, or a curved arc, avoids this — most EDA tools default to it for exactly this reason, even though it's more a manufacturing-consistency habit than a strict electrical requirement at typical trace widths.
• Via stitching for return-path continuity. Where a signal layer changes reference plane at a via — say, moving from a layer referenced to ground to one referenced to power — placing a stitching via nearby that connects the two planes gives the signal's return current a short path across the plane transition instead of forcing it to detour. Signal integrity in PCB design covers why an uninterrupted return path matters for both signal quality and EMI.
• Copper pour on unused board area. Filling otherwise-empty routing area with a copper pour tied to ground is common practice, both to reduce plane impedance further and to even out copper distribution across the board for etching and thermal consistency. It's a supplement to a properly planned ground plane, not a substitute for one.
• Differential pair routing and length matching. A differential pair (USB, Ethernet, many SerDes links) has to be routed with the two traces kept a consistent, controlled distance apart for the pair's controlled impedance, and length-matched to a tight tolerance so both legs arrive at the receiver together — a mismatch introduces timing skew that degrades the pair's common-mode rejection. Length matching is usually done with a serpentine or accordion-style meander added to the shorter leg. See routing controlled-impedance and differential pairs in KiCad for how a specific EDA tool implements the diff-pair router and length-tuning mode.
• Fanout before general routing on fine-pitch parts. A fine-pitch BGA has to be escape-routed — each ball connected out to a via — before general board routing can proceed, because the fanout pattern sets how much routing channel is left to pass under the package. See BGA fanout and escape routing for the dogbone pattern this typically uses and how ball pitch drives via strategy.

Manual Routing, Autorouting, and Interactive Assist

Most professional layouts are routed manually, or autorouted and then substantially hand-cleaned, rather than left as raw autorouter output. An autorouter connects nets algorithmically according to whatever design rules it's given, which is fast on simple, low-density boards but rarely produces a result that's actually optimal once length matching, current-carrying paths, or impedance-sensitive nets are involved — it has no concept of which nets matter more than others unless that's explicitly configured net by net.

Modern EDA tools sit somewhere between the two extremes with interactive routing assist: push-and-shove routing that nudges existing traces aside as a new one is drawn instead of stopping at the first collision, and dedicated differential-pair routers that keep both legs of a pair spaced and length-matched automatically as they're drawn. These tools speed up manual routing considerably without handing routing judgement over to an algorithm the way full autorouting does, which is why they, rather than autorouting, are the standard workflow on anything beyond a simple board.

Practical Examples

A microcontroller's crystal oscillator traces are typically routed first and kept short, direct, and clear of other signals, because the crystal circuit is sensitive to parasitic capacitance and noise coupling. A beginner mistake is to route it last, by which point the only remaining path is long and runs alongside several other signals.

On a board with a high-speed differential pair (USB, for instance), routing has to maintain consistent trace width and spacing for the controlled impedance the protocol requires, keep the two traces length-matched, and avoid routing vias or layer changes that would introduce impedance discontinuities. An autorouter handles none of this well without significant manual rule configuration first.

A board with a fine-pitch FPGA or DDR memory BGA presents the opposite kind of challenge: before any of the surrounding signal routing can even begin, every ball under the package has to be fanned out to a via, and at a 0.5 mm pitch or finer, that fanout alone can dictate the board's minimum layer count. General routing is effectively planned around the fanout pattern, not the other way round.

Design Considerations

• Route critical and constrained nets before general-purpose ones. Clocks, high-speed buses, and anything length- or impedance-sensitive should get first claim on the cleanest, most direct paths.
• Keep return paths in mind, not just the forward signal path. A signal routed over a split or gap in its reference plane has a degraded return path even though the forward trace looks fine. See signal integrity in PCB design for how return-path breaks connect to reflections, crosstalk, and EMI.
• Use vias deliberately, not just where convenient. Every layer change adds inductance and a potential impedance discontinuity, which matters far more on a high-speed net than a low-speed one. See types of PCB vias for how via choice affects this.
• Size traces for their actual current, not by habit. A trace that's too narrow for its load current will overheat under sustained load; see how to calculate PCB trace width for current capacity.
• Run DRC continuously through routing, not just at the end. A clearance or width violation is far cheaper to fix the moment it's introduced than to find in a batch just before fabrication output. See what are PCB design rules (DRC)? for how design rules are set and checked.
• Widen spacing on high-voltage nets beyond the standard DRC minimum where required. Routing that's perfectly manufacturable can still fail a safety requirement if the creepage and clearance distance between a high-voltage net and everything around it hasn't been checked against the applicable standard; see PCB creepage and clearance distances.
• Dense or high-speed routing: complex routing challenges, including mixed signals, controlled-impedance differential pairs, and tight pitch BGAs, are where professional PCB layout makes the biggest difference over a self-taught approach.

Common Mistakes

• Routing power and ground as thin traces instead of planes on boards with more than two layers, creating unnecessary voltage drop and a poor return path for every signal referenced to that net.
• Leaving the most sensitive nets (oscillators, high-speed differential pairs) for last, by which point the cleanest routing paths have already been used by less-critical signals.
• Adding vias freely on high-speed nets without considering the impedance discontinuity and added inductance each one introduces.
• Treating autorouter output as finished rather than as a starting point: autorouted boards almost always need manual cleanup on critical nets before they're production-ready.
• Leaving DRC until the very end of routing instead of running it continuously, turning what should be a handful of small fixes into a large cleanup pass right before a fabrication deadline.