How Do You Calculate PCB Trace Width for Current Capacity?

Detailed Explanation

A copper trace heats up as current flows through it, due to its resistance, and the question a trace-width calculation answers is: how wide does this trace need to be to carry a given current without exceeding an acceptable temperature rise? The relevant variables are the trace's cross-sectional area (width multiplied by copper thickness/weight), the ambient and acceptable maximum temperature, and whether the trace sits on an external layer (open to air, dissipating heat more easily) or an internal layer (surrounded by dielectric, dissipating heat far less efficiently).

IPC-2152 is the current standard reference for this calculation, superseding the older IPC-2221 charts that many designers still default to out of habit. IPC-2152's data was derived from more representative thermal testing of real board constructions and generally produces different results than IPC-2221 (often more conservative for internal layers), which is why current guidance recommends it specifically for anything where getting this right actually matters.

How the Calculation Actually Works

A trace-width calculation has four inputs, and skipping any one of them makes the result unreliable:

1. Target current. The worst-case sustained current the trace will carry, not the typical or average current. Use the fault or peak-continuous condition if the trace has to survive it.
2. Copper weight. The trace's thickness, expressed in ounces per square foot (oz), which sets the cross-sectional area for a given width.
3. Layer type. External (top/bottom, open to air) or internal (buried between layers, insulated by dielectric on both sides).
4. Acceptable temperature rise. How far above ambient the trace is allowed to get under that current. This is a design decision, not a fixed constant (see the FAQ below).

In practice, almost nobody works through the IPC-2152 curves by hand. The standard's data is normally applied through a calculator tool (Saturn PCB's toolkit is a common free option) or built directly into ECAD trace and impedance planning features. The manual charts exist mainly for verifying a tool's output or for reference when a tool isn't available.

Copper Weight and Trace Thickness

Copper weight is usually specified in ounces per square foot, which corresponds to a fixed thickness rather than a fixed width:

These are the standard's typical nominal values. Actual finished copper thickness varies slightly by fabricator and process, so treat them as a starting point for the calculation rather than a guaranteed figure, and confirm with your fabricator's stack-up documentation for a tight design.

Practical Examples

A 1A signal trace on an external 1oz-copper layer can typically be quite narrow, well under a millimetre, with negligible temperature rise, which is why most low-current signal routing doesn't need a trace-width calculation at all.

A 5A power trace feeding a motor driver or charging circuit is a different story: at 1oz copper on an external layer, IPC-2152 data suggests a trace width in the range of several millimetres to keep temperature rise within a reasonable margin, and the same current on an internal layer would need to be wider still: exactly the kind of calculation worth running explicitly rather than guessing, since undersizing it leads to a trace that runs hot under sustained load and degrades over time.

The table below illustrates how the same current demands very different widths depending on layer type and copper weight (approximate, IPC-2152-based figures at a 20°C rise; always confirm with a calculator against your actual stack-up rather than reusing these as exact values):

The pattern that matters more than any single number: doubling copper weight roughly halves the width needed for the same current and temperature rise, and an internal layer typically needs somewhere around 1.5–2x the width of an equivalent external trace, because it has no direct path to shed heat into open air.

When to Use a Plane or Pour Instead of a Trace

Once calculated current-carrying width starts competing with routing space, or the current is high enough that a single routed trace becomes impractical, it's usually better to move the current path onto a copper plane or a pour rather than keep widening a trace:

• A dedicated plane or wide pour spreads current over a much larger cross-section and gives the heat a larger area to dissipate into, which is why most board designs move high-current rails (main power input, motor phase currents, battery charge paths) onto planes rather than traces once current climbs into the several-amp range.
• A pour still needs the same current-capacity thinking as a trace. A pour that necks down to a narrow isthmus around a component or via field can create a bottleneck that's easy to miss visually but behaves electrically like an undersized trace at that pinch point.
• Multiple parallel traces are sometimes used as an alternative to a single wide trace or plane, particularly where a plane isn't available on that layer, but the current doesn't split evenly unless the parallel paths have genuinely matched resistance, which is an easy way for one trace to end up running hotter than its neighbours.

See PCB power and ground plane design for how to lay out planes themselves, and what is a PCB stack-up for how layer count and copper weight get decided together at the stack-up level.

Design Considerations

• Always specify layer type (internal/external) and copper weight before calculating. Both materially change the required width for the same target current. See what is a PCB stack-up for how copper weight is chosen and specified at the stack-up level, before individual trace widths are calculated.
• Use IPC-2152 rather than IPC-2221 for any current-capacity decision that matters. The older standard's free-air test basis tends to understate the width needed on real, internal-layer constructions.
• Don't rely on trace width alone for high-current paths. Consider a dedicated plane or copper pour instead of a routed trace once current gets high enough that trace width alone becomes impractically wide.
• Account for via current capacity too, not just trace width, wherever a high-current path changes layers: a via sized only for routing convenience can become the actual bottleneck. See types of PCB vias.
• High-current design review: For power-dense boards where trace and via sizing directly affects long-term reliability, professional PCB design includes a current-capacity and thermal review as part of the layout process.

Common Mistakes

• Defaulting to an old IPC-2221 chart or a rule-of-thumb width without checking it against the actual layer type and copper weight in the real stack-up.
• Sizing a power trace for routing convenience rather than calculated current capacity, then discovering excessive temperature rise during a thermal test.
• Forgetting that internal-layer traces need to be wider than external traces for the same current, and applying an external-layer width assumption throughout the board.
• Ignoring the current capacity of a via in a high-current path, leaving a narrow via as the actual thermal bottleneck on an otherwise correctly-sized trace.
• Picking a temperature-rise target without checking it against nearby component ratings: a trace calculated for a 20°C rise can still overheat a temperature-sensitive part mounted right beside it.
• Letting a copper pour neck down to a narrow isthmus around vias or component keep-outs, creating an unintended current bottleneck that a visual routing check won't catch but a current-capacity check will.
• Splitting a high-current path across multiple parallel traces without confirming their resistances actually match, so one trace ends up carrying disproportionately more current, and more heat, than the others.