How Do You Design a USB-C Port on a PCB?

Detailed Explanation

USB-C replaces USB Type-A, Mini-USB, and Micro-USB connectors with a single reversible connector that carries power, USB 2.0 data, USB 3.x SuperSpeed data, DisplayPort Alt Mode, and USB Power Delivery. Implementing USB-C correctly on a PCB requires understanding the Configuration Channel (CC) lines, ESD protection, and differential pair routing. Getting any of these wrong produces a device that fails to enumerate, charges at the wrong current, or fails ESD compliance testing. For background on the USB protocol itself, see What Is USB?.

USB-C Connector Pin-Out

A full-featured USB-C connector has 24 pins:

For embedded IoT and product firmware applications that need USB 2.0 only, you typically route: VBUS, GND, CC1, CC2, D+, D–. The SuperSpeed pairs and SBU lines can be left unconnected.

CC Lines and Pull-Down Resistors

The CC (Configuration Channel) lines are how USB-C devices identify their role and request power. The rules (from the USB Type-C specification):

• UFP (device): place a 5.1 kΩ pull-down resistor from both CC1 and CC2 to GND. This signals to the connected host that a sink (device) is present and that it can draw default USB current.
• DFP (host/charger): place pull-up resistors (Rp) from CC1 and CC2 to VBUS:
  • Rp = 56 kΩ → advertises 5 V / 500 mA (USB 2.0 default) or 5 V / 900 mA (USB 3.x default)
  • Rp = 22 kΩ → advertises 5 V / 1.5 A
  • Rp = 10 kΩ → advertises 5 V / 3 A
• DRP (dual-role): alternate between UFP and DFP signalling until a role is negotiated

For a simple UFP device (no USB PD):

              USB-C Connector
              ┌──────────────┐
VBUS ─────────┤ VBUS         │
              │              │
CC1 ──┬───── ┤ CC1          │
    5.1kΩ    │              │
      └─ GND ┤              │
              │              │
CC2 ──┬───── ┤ CC2          │
    5.1kΩ    │              │
      └─ GND ┤              │
              │              │
D+ ─────────┤ D+           │
D– ─────────┤ D–           │
GND ─────────┤ GND          │
              └──────────────┘

You must place 5.1 kΩ resistors on both CC1 and CC2. Since the USB-C cable can be inserted either way, either CC pin could be the active one — without both pull-downs, the device fails to enumerate in one cable orientation.

If using a USB PD controller IC (FUSB302, STUSB4500, IP2721, etc.), the PD controller handles the CC lines internally — do not add separate 5.1 kΩ pull-downs in that case. The PD controller manages CC signalling for power role negotiation.

ESD Protection

USB ports are exposed to the full electrostatic discharge threat of the outside world: human body model discharges from users handling the cable, cable events, and field exposure in industrial environments. IEC 61000-4-2 Level 4 (±8 kV contact, ±15 kV air) is the standard ESD requirement for USB ports on end-user-accessible devices.

ESD protection devices must be placed as close to the connector as possible — before any series resistors or ferrite beads on the signal lines. The placement rule: connector → ESD device → everything else.

Critical specifications for USB ESD protection:

High capacitance on the D+/D– lines degrades signal integrity — a 2 pF capacitor on a 480 Mbps USB 2.0 line introduces measurable signal degradation, and 1 pF on a 5 Gbps SuperSpeed line is highly problematic.

Commonly used ESD protection ICs:

• PRTR5V0U2X (Nexperia, SOT363): dual-channel, 0.35 pF per line, ±8 kV, covers D+ and D–
• TPD2S300 (Texas Instruments, SOT23-8): covers D+, D–, CC1, CC2, includes integrated 5.1 kΩ CC pull-downs — single IC replaces ESD devices and CC resistors for UFP applications
• USBLC6-2SC6 (STMicroelectronics, SOT23-6): dual-channel, 0.4 pF, ±8 kV, covers D+ and D–

The TPD2S300 is particularly convenient for embedded devices: it integrates ESD protection and CC resistors in one package, reducing BOM complexity.

VBUS protection: VBUS can surge to 20 V during USB PD handoff events or connector hot-plug transients. Add a TVS diode (rated for at least 25 V standoff) from VBUS to GND at the connector, and a 100 nF + 10 µF decoupling capacitor (X7R/X5R ceramic, 25 V rated) immediately adjacent to the connector.

D+/D– Differential Pair Routing

USB 2.0 at Full Speed (12 Mbps) or High Speed (480 Mbps) requires D+ and D– to be routed as a controlled-impedance differential pair:

• Target impedance: 90 Ω differential (45 Ω each trace to the reference plane, single-ended)
• Length matching: D+ and D– must be matched in length — the intra-pair skew must be kept below approximately 150 ps for HS USB (roughly 15 mm at FR4 propagation speed)
• Keep the pair together: no vias between D+/D– and the USB transceiver if avoidable; each via adds approximately 0.1–0.2 pF of capacitance
• Reference plane continuity: route over an unbroken reference plane (GND pour); avoid anti-pads from vias crossing under the differential pair
• Minimise stub length: any stub — a short trace that branches off the main signal path — creates a reflective discontinuity. Route D+/D– directly from connector to ESD device to transceiver with no branches

For USB 3.x SuperSpeed (5 Gbps, 10 Gbps), the target differential impedance is 85 Ω for the TX/RX pairs. Length matching is more critical (< 100 µm pair-to-pair skew for 10 Gbps). SuperSpeed routing typically requires a professional controlled-impedance PCB stackup. See Signal Integrity in PCB Design for transmission line fundamentals.

For PCB stackup impedance calculation, confirm the 90 Ω differential trace width/spacing with your PCB fabricator using their actual dielectric constant and copper weight — calculators using nominal FR4 Er values can be off by 10–15%.

USB Power Delivery Basics

Without USB PD, a UFP device with 5.1 kΩ CC pull-downs can draw:

• 5 V / 500 mA (USB 2.0 default current)
• 5 V / 900 mA (if the DFP pull-up Rp signals 1.5 A or 3 A capability, a UFP can draw up to 900 mA on USB 3.x links with current-mode CC detection)

For higher power (charging a battery at 2 A+, powering a display, driving 12 V or 20 V loads), USB PD negotiation over the CC lines is required:

A USB PD controller IC (FUSB302 from ON Semi, STUSB4500 from STMicro, IP2721 from Injoinic for sink-only designs) manages the CC line protocol messaging and drives a downstream DC-DC converter to regulate the negotiated voltage. For embedded products that need to receive power at 9 V or 12 V (for local regulation to 5 V or 3.3 V), the STUSB4500 is a common choice: it stores up to three PDOs in NVM, automatically negotiates the highest matching PDO from the source, and exposes the result via I2C. See How Does a Buck Converter Work? for the downstream DC-DC conversion.

Important: VBUS decoupling capacitors must be rated for the maximum PD voltage (20 V for standard PD, 28 V for EPR), not just 5 V. A 10 µF 10 V ceramic capacitor on VBUS is a latent reliability failure in any product supporting USB PD.

Design Considerations

• Use the TPD2S300 if you just need USB 2.0 UFP power + data. It integrates the CC pull-downs and ESD protection in a single SOT23-8 IC, reducing component count and simplifying placement. Zeus Design includes USB-C connector layout, impedance-controlled routing, and ESD protection placement as standard in PCB design engagements for IoT and embedded products.
• Place the ESD device before everything else. The shortest path from the connector pin to the TVS clamp is the most effective path. Routing connector pads to a faraway ESD IC first passes through unprotected copper that acts as an antenna during ESD events.
• Use a test point on VBUS and the CC lines during bring-up. CC line voltages diagnose most connection and enumeration problems: 0 V on both CC lines means no pull-down resistors are connected; 1.6 V on one CC and floating on the other indicates correct UFP detection with a DFP Rp of 56 kΩ.
• Shield-to-earth connection: if the PCB has chassis or earth access, connect the USB-C connector shield to earth ground via a 0 Ω resistor or capacitor (1–10 nF) in series. This provides an EMC return path without creating a DC ground loop between isolated USB ground and chassis.
• USB PD requires a Buck converter rated for the input voltage range. If the device requests 20 V via USB PD, the downstream voltage regulator must handle 20 V input — not just 5 V. Design the power path for the maximum negotiated voltage, not the typical voltage.

Common Mistakes

• Only populating CC1 pull-down and leaving CC2 floating: the device works in one cable orientation but fails to enumerate in the other. Always populate both CC1 and CC2 with 5.1 kΩ to GND for a UFP without PD.
• Using 10 kΩ or 22 kΩ on the CC lines instead of 5.1 kΩ: these values are the Rp pull-ups used on the DFP (host) side. A UFP with 22 kΩ on CC will confuse connected hosts — some hosts will misidentify the port as a 1.5 A DFP rather than a UFP. Use exactly 5.1 kΩ (±5% tolerance is acceptable) for the UFP pull-downs.
• VBUS capacitors rated only for 5 V: a USB PD charger that negotiates 20 V will charge VBUS to 20 V before the PD controller brings it to the negotiated voltage. Capacitors with a 10 V or 16 V rating will be overvoltaged. Always rate VBUS decoupling to at least 25 V for any design that might connect to a USB PD source.
• Routing D+/D– without impedance control: casual routing that leaves D+/D– trace widths to the PCB manufacturer's default will produce non-90 Ω impedance, causing reflections that degrade USB signal eye diagrams. Specify the differential impedance in the PCB fabrication note and request an impedance-controlled stackup.
• Placing ESD protection downstream of series resistors or ferrite beads: series elements reduce the ESD clamp's effectiveness by inserting impedance between the external exposure and the TVS path. The connector → ESD device sequence must be maintained with no passive components in between.
• Assuming a standard USB charger provides consistent VBUS voltage: some legacy chargers and USB ports output VBUS outside the USB specification range (5 V ±5% = 4.75–5.25 V). The DC-DC downstream of VBUS should operate correctly with VBUS in the range 4.5–5.5 V at a minimum; do not assume exactly 5.0 V.