What Is Power Factor Correction (PFC) and When Do You Need It?

Detailed Explanation

Any device powered directly from mains AC eventually rectifies that AC into a DC bus before a switching converter can use it. How that rectification stage draws current from the mains — not just how much power it consumes, but the shape of the current waveform — is what power factor correction addresses.

The Problem: Why a Simple Rectifier Front End Draws Bad Current

A basic offline power supply front end is a bridge rectifier followed by a large electrolytic bulk capacitor. The capacitor only recharges when the rectified mains voltage exceeds the capacitor's current voltage — which happens only near the peak of each AC half-cycle. The result is that the supply draws current in short, high-amplitude pulses near the waveform peaks and draws almost no current the rest of the cycle.

This pulsed current waveform is rich in harmonics of the mains frequency (50 Hz in Australia): third, fifth, seventh harmonic and beyond, each carrying real energy that does no useful work but does distort the voltage waveform seen by every other device sharing that mains circuit, adds unnecessary RMS current (and therefore I²R losses) throughout the building's wiring, and can trip or stress upstream protective devices sized for the equipment's nominal RMS current rather than its actual peak-heavy current draw.

Power factor quantifies this: it's the ratio of real power (the power actually doing useful work) to apparent power (RMS voltage × RMS current). A rectifier-and-bulk-capacitor front end without PFC typically has a power factor around 0.5–0.7 — meaning the supply is drawing significantly more RMS current from the mains than the real power it uses would require if the current were a clean sine wave in phase with the voltage.

How Active PFC Works

Active PFC inserts a controlled switching stage — almost always a boost converter — between the rectifier and the bulk capacitor. Unlike a normal boost converter regulating to a fixed output, a PFC boost stage's control loop has two objectives running simultaneously:

1. Current shaping (the fast inner loop): the controller forces the inductor current to track the shape of the rectified input voltage, so the supply draws current that is (approximately) a scaled, in-phase replica of the input voltage waveform — behaving, from the mains's perspective, like a resistor rather than a peak-current-pulse load.
2. Bulk voltage regulation (the slow outer loop): the boost stage's output (the DC bus that feeds the downstream isolated converter, typically a flyback or LLC stage) is regulated to a fixed DC voltage, typically 380-400V, well above the peak of the highest rectified input voltage the universal-input range produces.

Because it's a boost converter, the PFC stage's output voltage must always be higher than the input's instantaneous peak across the full universal input range — this is why PFC-preregulated offline supplies commonly run their downstream isolated stage from a ~380-400V DC bus rather than directly from the raw rectified mains.

Common PFC control modes include continuous conduction mode (CCM) average-current-mode control (the standard for supplies above roughly 150-300W, offering the lowest input current distortion) and critical conduction mode / boundary conduction mode (BCM) control (simpler, used in lower-power designs, where the inductor current is allowed to just reach zero each switching cycle). See How Does a Boost Converter Work? for the underlying boost topology mechanics that a PFC stage builds on — the key difference is that a PFC controller continuously varies its target current within each half-cycle to track the input voltage, rather than regulating to a single fixed current or voltage setpoint.

Passive PFC

Passive PFC uses a large mains-frequency inductor (sometimes combined with a valley-fill capacitor arrangement) placed in series before the bulk capacitor, spreading the charging current pulse over more of the AC cycle without any active switching. It reaches a power factor of roughly 0.7-0.85 — a real improvement over an uncorrected rectifier front end, but well short of what active PFC achieves, and the mains-frequency inductor required is physically large and heavy compared to the high-frequency magnetics an active PFC stage uses. Passive PFC survives mainly in cost- and simplicity-sensitive designs where the applicable harmonic limit doesn't require active correction.

Common PFC Controller ICs

Why This Matters for Compliance

IEC 61000-3-2 (adopted in Australia as AS/NZS 61000.3.2) sets limits on the harmonic current a piece of equipment is permitted to inject into the mains supply, categorising equipment into classes with different limit tables. Mains-connected products above a power level that varies by equipment class and current waveform — commonly cited as approximately 75W for the equipment classes many consumer and IT products fall under — typically cannot meet these limits with a simple rectifier-and-bulk-capacitor front end, making active PFC a practical requirement rather than an optional efficiency feature. This sits within the same regulatory framework covered in Which EMC Standard Applies in Australia? and the broader RCM certification process — a product's harmonic current emissions are tested and reported alongside its conducted and radiated emissions during compliance testing, and failing IEC 61000-3-2 blocks certification exactly like a radiated emissions failure would.

Because this power-level threshold, exact class assignment, and the specific limit tables can be nuanced for a given product category, confirm applicability against the current edition of the standard for your specific product type rather than relying on the "75W" figure as a universal rule.

For power supply design that needs to meet mains harmonic and EMC compliance from the outset — PFC stage selection, magnetics specification, and the full compliance test plan — Zeus Design designs offline and mains-connected power supplies through to certification.

Design Considerations

• Size the PFC boost inductor for the full universal-input range, not just nominal mains. A universal-input design (85-265VAC) sees its widest inductor current swing at the lowest input voltage and highest load — verify saturation current and core loss at that worst-case corner, not just at 230VAC nominal.
• The downstream converter's input voltage is the PFC bus voltage, not raw rectified mains. Because the PFC stage regulates its output to a fixed DC bus (typically 380-400V), the isolated stage that follows it (flyback, LLC, forward converter) is designed for a much narrower, regulated input range than an equivalent non-PFC design working from raw rectified universal-input mains — this can simplify the downstream converter's design margin.
• EMI filtering is still required in addition to PFC. PFC addresses low-frequency harmonic current distortion (IEC 61000-3-2); it does not address the high-frequency conducted and radiated emissions from the PFC stage's own switching action, which still require a conventional input EMI filter (common-mode choke, X and Y capacitors) — see How to Reduce PCB EMI.
• Combo (PFC + PWM) controller ICs reduce component count but couple the two control loops' design margins. For mid-power offline designs, a single IC handling both the PFC boost stage and the downstream flyback/LLC control simplifies the bill of materials, but datasheet application circuits should be followed closely — the interaction between the PFC bus ripple and the downstream converter's line-rejection performance is a common source of subtle design errors when deviating from the reference design.

Common Mistakes

• Assuming a low-power product is exempt from IEC 61000-3-2 entirely. Even products below the power threshold where active PFC becomes a practical necessity are still subject to IEC 61000-3-2's limits for their equipment class — a simple rectifier-and-bulk-capacitor front end may or may not pass depending on the specific class and load current waveform. Verify against the applicable limit table during design, not just at compliance test time.
• Treating PFC as purely a compliance checkbox and ignoring its interaction with hold-up time. The PFC bulk capacitor's voltage also determines how long the supply can ride through a brief mains interruption (hold-up time) before the downstream converter's input voltage sags out of regulation. Sizing the bulk capacitor for harmonic compliance alone, without checking hold-up time requirements, is a common oversight that surfaces late in a design cycle.
• Underestimating PFC inductor core loss at low-line, full-load operation. The PFC boost inductor sees its highest RMS and peak current at the lowest input voltage in the universal-input range (85VAC) at full load — a design validated only at 230VAC nominal input can run significantly hotter, or even saturate, at 85VAC full-load operation.
• Not budgeting PFC stage efficiency loss in the overall power budget. An active PFC stage typically adds 1-3 percentage points of conversion loss compared to a non-PFC front end — for a battery-backed or thermally constrained design, this loss (and the resulting heat) needs to be accounted for in the enclosure thermal design, not discovered after board bring-up.