SMPS

Switch-mode power supplies (SMPS) convert one DC voltage to another by rapidly switching energy through an inductor or transformer, achieving far higher efficiency than a linear regulator at the cost of more design complexity and switching noise. This subtopic covers the non-isolated and isolated switching topologies, how to choose between them, and the PCB layout practices that determine whether a switching design actually meets its efficiency and EMC targets on real hardware.

What Is SMPS Design?

This subtopic covers switch-mode power conversion at the topology and implementation level: how buck, boost, and flyback converters actually transfer energy; how to choose the right topology for a given input/output voltage relationship; and the PCB layout rules that keep a switching design's efficiency, noise, and EMC performance close to its datasheet numbers. For the higher-level choice between a linear regulator and a switching regulator, see Linear vs Switching Regulator in the parent Power Electronics topic.

This subtopic is part of the Power Electronics topic.

Why SMPS Design Matters

• The wrong topology loses regulation at exactly the wrong moment — a single Li-ion cell discharging from 4.2 V to 2.5 V through a 3.3 V rail crosses the output voltage mid-discharge; a pure buck or pure boost will fail to regulate at that crossing, and only a buck-boost topology handles the full range.
• PCB layout determines whether a converter meets its datasheet efficiency and EMC numbers at all — the switching loop's area sets radiated emissions directly, and a datasheet reference design copied without understanding the loop-area principle can miss both efficiency and compliance targets.
• Component derating under real operating conditions is not optional — ceramic output capacitors lose significant capacitance under DC bias, and inductors saturate below their nameplate current rating as temperature rises; both are common causes of field failures that never show up on the bench at room temperature.
• Isolated and non-isolated topologies solve different problems — a design that needs galvanic isolation (mains-connected equipment, medical devices, sensor interfaces with hazardous voltage) cannot use a non-isolated buck or boost regardless of how well-suited the voltage ratio looks.

Key Concepts

• Duty cycle — the fraction of the switching period the main switch is on; in steady state, duty cycle directly sets the buck converter's voltage conversion ratio (D ≈ Vout / Vin).
• Continuous vs discontinuous conduction mode (CCM/DCM) — whether inductor current stays above zero throughout the switching cycle (CCM) or falls to zero before the next cycle starts (DCM); the converter's control dynamics differ significantly between the two.
• Switching loop area — the physical PCB loop carrying the converter's pulsed switching current; minimising this loop's area is the single highest-leverage PCB layout decision for both efficiency and radiated EMI. See buck converter PCB layout.
• Galvanic isolation — a flyback converter's transformer provides electrical isolation between input and output, unlike the shared-ground buck and boost topologies; required whenever the output must be isolated from a hazardous or noisy input rail. See how a flyback converter works.
• Inductor saturation current (Isat) — the current at which a switching inductor's inductance collapses, causing loss of current control; must be derated for the worst-case peak current and operating temperature, not just the nominal DC load. See inductor types and saturation current.

Common Mistakes

• Choosing a buck-boost topology when a simple buck or boost would do — buck-boost topologies add switching-node complexity, mode-transition behaviour, and typically lower efficiency; only use one when the input and output voltage ranges genuinely overlap.
• Sizing the output capacitor by nameplate capacitance alone — ceramic capacitors lose a substantial fraction of their rated capacitance under DC bias (a 4V-rated 22 µF 0402 part can measure closer to 10 µF at 3.3 V); undersized effective capacitance shows up as excess ripple or stability margin loss that isn't visible from the part number alone.
• Copying a reference design's layout without understanding the switching loop — a datasheet layout works because of its loop-area and grounding choices, not just its component placement; scaling or mirroring it without preserving those choices can silently degrade both efficiency and EMC performance.
• Underestimating peak inductor current at high load — the ripple current adds to the DC load current to set the actual peak the inductor must handle without saturating; using Isat ≈ Iout_max instead of Isat ≥ 1.3× Ipeak is a common design error that only fails under worst-case load and temperature.

Common Questions

When do I actually need a buck-boost instead of a buck or boost?

Only when the input voltage range can be either above or below the output voltage during normal operation. The clearest example is a single-cell Li-ion battery (4.2 V down to 2.5–3.0 V) powering a 3.3 V rail: the cell starts above 3.3 V and ends below it, so a pure buck or boost will lose regulation partway through discharge. If the input is always safely above or always safely below the output across its full range, the simpler buck or boost topology is the better choice. See DC-DC converter topology selection for the full decision framework, including SEPIC and 4-switch buck-boost options.

Why does my buck converter's efficiency not match the datasheet?

The most common causes, in rough order of impact: PCB switching loop area larger than the reference design (adds parasitic inductance and ringing losses), an inductor with higher DCR than the reference design's part, insufficient input/output capacitance causing the converter to work harder to maintain regulation, and running well outside the datasheet's tested load or input voltage range (light-load efficiency in particular is often much lower than the peak-efficiency number quoted on the front page). See buck converter PCB layout for the layout-specific causes.

Do I need an isolated topology for my design?

Only if the application genuinely requires galvanic isolation between input and output: mains-connected equipment (safety isolation from line voltage), medical devices (patient safety isolation), or any design where a fault on one side must not propagate to the other. If both sides share a common ground reference safely, a non-isolated buck, boost, or buck-boost is simpler, cheaper, and more efficient. See how a flyback converter works for the isolated-topology mechanics. Zeus Design designs switch-mode power supplies, including isolated and multi-output designs, for commercial products.

Knowledge Base

How Switching Converters Work

• How Does a Buck Converter Work? — the switching cycle, energy transfer, duty cycle, and continuous vs discontinuous conduction mode
• How Does a Boost Converter Work? — step-up energy transfer, current and voltage relationships
• How Does a Flyback Converter Work? — transformer-based energy storage, galvanic isolation, turns ratio, snubber design, and optocoupler feedback
• How Does an LLC Resonant Converter Work? — the resonant tank and gain curve, how zero-voltage switching eliminates hard-switched turn-on loss, and frequency-based regulation versus duty-cycle control

Topology Selection

• Buck, Boost, or Buck-Boost? How to Choose a DC-DC Converter Topology — the voltage-range rule, SEPIC vs 4-switch designs, efficiency trade-offs, and common mistakes
• How Does a Multiphase (Interleaved) Buck Converter Work for High-Current Point-of-Load Rails? — interleaving multiple buck phases for CPU/FPGA/ASIC core rails, ripple cancellation, phase count trade-offs, and current sharing via DCR sensing

PCB Layout

• How Should You Lay Out a Buck Converter PCB? — switching loop minimisation, input capacitor placement, and EMC-driven layout decisions

Control Loop Design

• Current-Mode vs Voltage-Mode Control: How Does SMPS Loop Compensation Actually Work? — the inner-loop/outer-loop architecture difference, Type II vs Type III compensation, and why current-mode control needs slope compensation above 50% duty cycle

Switching Devices

• GaN vs Silicon MOSFET: How Do You Choose for a Power Design? — how GaN's near-zero reverse-recovery charge enables higher switching frequency, and the gate-drive-loop and CMTI margin it costs versus a silicon MOSFET (secondary coverage — see the Power Electronics topic for the full page)

Mains and Compliance-Driven Design

• What Is Power Factor Correction (PFC) and When Do You Need It? — active vs passive PFC, how the PFC boost stage works, common controller ICs, and the IEC 61000-3-2 compliance requirement it addresses

Forum Discussions

• TPS63020 output drooping 200 mV and ringing as battery drains through 3.3 V — mode transition issue? — buck-boost mode-transition instability in the Vin≈Vout crossover region, traced to output capacitor DC bias derating
• TPS562201 output sags and enters hiccup mode above 1.8 A — inductor saturation current vs peak current, soft saturation onset below rated Isat, and the derating rule for inductor selection