How Should You Place Decoupling Capacitors on a PCB?

Detailed Explanation

A decoupling (or bypass) capacitor's job is to act as a local, fast-responding charge reservoir for an IC's power pin, supplying the brief, high-frequency current spikes that occur when internal logic switches. That current is something the board's external power supply and power plane, both relatively slow and inductive at high frequency, can't deliver fast enough on their own. The capacitor only does this job well if the loop it forms (power pin, through the capacitor, to ground, and back to the IC's ground pin) is physically short and low-inductance, because that loop's inductance directly limits how quickly the capacitor can respond.

This is why "decoupling capacitor placement" is really a routing-loop problem, not just a "put a capacitor somewhere on this net" problem. A capacitor that's electrically connected to the right power pin but placed several centimetres away, or connected through a long, narrow trace instead of a short hop to a ground plane via, provides far less effective decoupling than the same capacitor placed immediately adjacent with a direct via down to ground.

Bulk, Local, and High-Frequency Decoupling

A single power rail commonly uses more than one tier of decoupling capacitor, and each tier does a different job:

These values are commonly used starting points, not fixed rules: the specific IC's datasheet is the authoritative source for which tiers it actually needs and at what values, since internal switching behaviour varies by part. A slow analog IC may need only a single local capacitor; a high-pin-count FPGA or fast digital IC often specifies all three tiers explicitly.

The tiers are complementary, not interchangeable: a large bulk capacitor placed close to the pin does not replace a local capacitor, because its larger physical size and internal construction typically give it higher equivalent series inductance (ESL), making it too slow to answer the fastest current transients even at short distance. Placement discipline matters more for the local and high-frequency tiers than for the bulk tier, precisely because their whole purpose is answering fast transients that a longer loop would blunt.

Placement Priority When Board Space Is Limited

When pin spacing or an underlying via field limits how many capacitors can sit directly next to a power pin, place them in this order of priority:

1. The smallest-value, fastest-responding capacitor goes closest to the pin. It's the one most sensitive to loop inductance, since its job is answering the fastest current edges.
2. The local (mid-frequency) capacitor goes next closest, still adjacent to the pin where possible.
3. The bulk capacitor can sit further away, on the same rail, since its role is supplying slower current over a longer time window where a few extra millimetres of trace inductance matters far less.

As a general guideline, the local and high-frequency capacitors are commonly placed as close as the component's footprint and adjacent pin spacing allow, often within a few millimetres for a fast digital IC. "As close as the layout allows" is the more reliable rule, though, since the acceptable distance depends on the specific IC's edge rates and the board's stack-up, not on any fixed number. Where a datasheet gives an explicit maximum trace length or loop-area figure, that value takes precedence over general guidance.

Via Placement and the Ground Return Path

How the capacitor's ground pad connects back to the ground plane affects the loop as much as the capacitor's distance from the power pin:

• A dedicated via placed immediately beside the ground pad, connected by the shortest possible trace stub, is the standard approach. It keeps the return path short while staying simple to fabricate and rework.
• Via-in-pad (a via placed directly inside the capacitor's land, then filled and capped for a flat solderable surface) removes the trace stub entirely, giving the shortest possible loop. It's common on high-pin-count BGA designs where board space under the package is tight, but it adds fabrication cost and typically requires the via to be filled and plated over, so it's usually reserved for designs where the loop-inductance benefit is worth that cost.
• Routing the ground connection through a trace to a via placed further away is the weakest option: it adds loop inductance proportional to the trace length, and is the layout equivalent of the "same net but physically distant" mistake described below, just on the ground side of the loop instead of the power side.
• Connecting directly to a copper plane fill rather than a thin trace, wherever the local copper allows it, reduces return-path inductance compared with a narrow trace, because a wider return path carries current with less series inductance than a narrow one.

A via with a thermal relief (a common default in many PCB CAD tools, added to ease hand soldering and rework) also carries more inductance than a solid, direct connection, because the thin spokes of the relief add series inductance the solid via doesn't have. For fast-switching decoupling vias, that's one of the more easily overlooked sources of added loop inductance. It's worth checking the CAD tool's default on that particular via rather than assuming it's safe.

Practical Examples

A microcontroller with several power pins typically needs a decoupling capacitor at each one, placed directly beside that specific pin, not one larger capacitor placed centrally and connected to all pins by a shared trace, which reintroduces the loop-length problem decoupling is meant to solve.

On a board where the same IC's decoupling capacitor was originally placed close but later got pushed aside during a placement revision to make room for a connector, the resulting longer loop can reintroduce power rail noise that wasn't present in the earlier layout, even though the capacitor, value, and net are all unchanged. This is exactly the kind of regression worth checking for explicitly after a placement change rather than assuming.

Design Considerations

• Place the capacitor on the same side of the board as the IC where possible, and route directly to the pin rather than via a long trace shared with other connections.
• Use a dedicated via straight down to the ground plane immediately beside the capacitor's ground pad, rather than relying on a routed ground trace, to minimise the return-path loop inductance.
• Follow the IC datasheet's recommended capacitor values and placement guidance when one is given. Manufacturers often validate specific values against their part's actual switching behaviour.
• Re-verify decoupling placement after any later layout revision that moves components around. A previously-correct placement can be silently degraded by an unrelated later change.
• Power integrity at scale: For production-targeted boards where power delivery noise directly affects system reliability, professional PCB layout services include power integrity review as part of the placement and routing process.

Common Mistakes

• Placing a decoupling capacitor "on the same net" but physically distant from the power pin it's meant to protect, defeating the short-loop requirement that makes it effective.
• Sharing a single capacitor across multiple power pins via a common trace instead of giving each pin its own capacitor with its own short loop.
• Connecting the capacitor's ground pad to a ground trace instead of a direct via to the ground plane, adding avoidable loop inductance.
• Assuming a single bulk capacitor placed near an IC can substitute for that IC's local decoupling capacitor, overlooking that a bulk capacitor's higher ESL makes it too slow to answer fast current transients regardless of how close it sits.
• Leaving a CAD tool's default thermal relief on a decoupling via without checking whether the added spoke inductance matters for that particular net.
• Assuming decoupling placement is "done" once and never re-checking it after a later placement revision moves the capacitor or the IC.