How Does a Multiphase (Interleaved) Buck Converter Work for High-Current Point-of-Load Rails?

Detailed Explanation

Modern CPU, FPGA, and ASIC core rails routinely draw tens to well over a hundred amps at voltages under 1V. That combination of high current, low voltage, and load steps that can swing from near-idle to full load in a handful of clock cycles is exactly where a single-phase buck converter runs out of headroom. A multiphase (interleaved) buck converter solves this by splitting the load across several parallel buck stages that share one output, rather than pushing the full current through one inductor and one pair of switches. See the SMPS topic for the full set of switching-converter guides, and how to choose a DC-DC converter topology for where multiphase buck fits relative to the other non-isolated topologies.

Why a Single-Phase Buck Runs Into Limits at High Current

A single-phase buck converter can be scaled up in current by using a larger inductor, a lower-Rds(on) MOSFET pair, and a bigger output capacitor bank, but each of those levers runs into a practical ceiling well before the current levels a CPU or FPGA core rail demands:

• Inductor and MOSFET thermal limits. Conduction losses scale with the square of current (I²R), so doubling the load current roughly quadruples the resistive losses in the inductor's DCR and the MOSFETs' Rds(on). At tens of amps through a single phase, that heat has to be removed from one hot spot on the board, which quickly becomes a thermal design problem rather than an electrical one.
• Output ripple. A single phase's inductor ripple current, and the resulting output voltage ripple, scales with the inductor value and switching frequency chosen for that one phase. Pushing more current through a single phase without a proportionally larger inductor increases ripple current, which either has to be absorbed by more output capacitance or accepted as looser regulation.
• Transient response. A microprocessor or FPGA core can step its current demand very quickly as it wakes cores or activates logic blocks. A single large inductor has more stored energy to release or absorb, but also a slower di/dt response to a sudden load step, since the achievable current slew rate is set by (Vin − Vout)/L on the way up and Vout/L on the way down. Point-of-load rails with fast, large transients need a control architecture that responds faster than a single-inductor design can.

Scaling a single phase to handle very high current also concentrates the design's parasitic inductance, EMI, and PCB copper requirements in one location, which makes switching-loop layout progressively harder as current climbs.

The Multiphase Topology

A multiphase buck converter uses N identical buck phases connected in parallel, each with its own inductor and switch pair, all sharing a single output capacitor bank and a single feedback node. A multiphase controller (or a set of coordinated PWM outputs from an MCU peripheral) drives each phase's switch pair at the same switching frequency, but with its turn-on instant evenly spaced across the switching period, 360°/N apart. A two-phase design interleaves at 180°, a three-phase design at 120°, a four-phase design at 90°, and so on.

Because every phase sees the same input voltage and regulates to the same output voltage, each phase only needs to supply Iload/N of the total load current under balanced operation. That's the core benefit: current is spread across N inductors and N sets of switches instead of one, so each phase's conduction losses and thermal stress drop roughly in proportion to the phase count, for a given total output current.

STM32 devices with an HRTIM peripheral are a common way to generate the precisely phase-shifted PWM outputs a multiphase design needs in firmware; see how do you use the STM32 HRTIM peripheral for how hardware-synchronized timing units keep multiple phases locked in phase without firmware re-triggering separate timers.

Ripple Cancellation From Interleaving

Interleaving does more than spread current. It also improves output ripple for a given amount of output capacitance. Each phase's inductor still produces its own triangular current ripple, but because the phases are time-shifted rather than switching in unison, their ripple currents arrive at the shared output node at different points in the cycle and partially cancel rather than adding directly.

The degree of cancellation depends on both the phase count and the duty cycle. In the idealized case, a two-phase design interleaved at exactly 180° achieves near-complete ripple current cancellation at the output when the duty cycle is close to 50%; away from that duty cycle, cancellation is only partial. The same principle extends to higher phase counts, where the near-complete cancellation points recur at duty cycles near k/N for integer k. In practice, component tolerances, layout asymmetry, and duty cycle values that fall between the ideal cancellation points mean designers should treat ripple cancellation as a substantial but partial reduction, not a guarantee of near-zero output ripple, and should verify actual ripple on the bench rather than relying solely on the idealized calculation.

There's a second, compounding effect: the ripple that does reach the output appears at N times the per-phase switching frequency rather than at the switching frequency itself. A higher effective ripple frequency is easier to filter with a given amount of output capacitance, since the capacitor's impedance at that frequency is lower. Together, partial ripple cancellation and the higher effective ripple frequency are why a well-designed multiphase converter commonly needs meaningfully less output capacitance than a single-phase design delivering the same total current at the same ripple target. The exact reduction depends on phase count, duty cycle, and how close the operating point sits to an ideal cancellation duty cycle, so it should be verified for the specific design rather than assumed from phase count alone.

Phase Count Selection Trade-offs

More phases are not automatically better. Each additional phase adds a controller output channel, a gate driver channel, an inductor, a pair of switches, and PCB area, and the controller itself needs to actively balance current across every phase present. Phase count selection is a genuine engineering trade-off, weighed against the specific rail's current and transient requirements:

Most commercial multiphase controller ICs support a fixed maximum phase count (commonly in the range of two to eight, though high-end VRM controllers for server and networking ASICs go higher). The design choice is which of the supported counts best matches the rail's peak current, transient step size, and available board area, not simply picking the maximum available.

Current Sharing and Current Sensing

Component tolerances mean no two phases are electrically identical: inductor DCR, MOSFET Rds(on), and even PCB trace resistance vary from phase to phase. Without active correction, these differences cause current to distribute unevenly, and the phase carrying the most current becomes the thermal and reliability limit for the whole converter, well before the sum of all phases reaches its rated total.

Multiphase controllers address this with a current-sharing (current-balancing) loop that measures each phase's current every switching cycle and trims that phase's duty cycle relative to the others so all phases converge toward an equal share of the total load. Two sensing approaches are commonly used:

• DCR sensing. An RC network placed across the inductor is sized so its time constant matches the inductor's own L/DCR ratio, making the voltage across the sense capacitor proportional to inductor current without adding a dedicated sense element in the power path. This is a common, low-cost approach because it avoids the extra conduction loss and cost of a series sense resistor, at the cost of sensing accuracy that depends on how well the RC time constant is matched to the inductor and how much the inductor's DCR itself varies with temperature.
• Dedicated current-sense resistors or sense amplifiers. A low-value series resistor (or an integrated current-sense MOSFET/amplifier) in each phase's power path gives a more direct and temperature-stable current measurement, at the cost of the resistor's own conduction loss and the board area and cost of N sense elements instead of one shared reference.

Which approach suits a given design depends on the accuracy required, the acceptable added conduction loss, and the specific controller IC's supported sensing methods. Check the controller's datasheet for what it expects and how much current-sharing accuracy it specifies across phases.

Transient Response Advantage

Beyond steady-state ripple and thermal spreading, multiphase controllers can respond to a sudden load step meaningfully faster than a single large-inductor design. Because each phase has a smaller individual inductor than an equivalent single-phase design would need for the same total current, each phase's current can slew faster in response to a step. Advanced multiphase controllers exploit this further with techniques that temporarily overlap or add phases during a fast load transient: briefly running phases outside their normal interleaved timing, or bringing shed phases back online immediately, rather than waiting for the next scheduled switching instant. This reduces the output voltage droop and overshoot a demanding CPU or FPGA core sees during a fast current step.

Practical Example

A 12V-input, 1.0V-output core rail rated for 80A average with 120A transient peaks is a realistic target for a four-phase design: each phase carries roughly 20A average, so per-phase inductor and MOSFET selection only needs to handle roughly a quarter of the total current rather than the full 80A a single-phase design would need to survive. Interleaving at 90° spacing pushes the dominant output ripple frequency to four times the per-phase switching frequency. At a 500 kHz per-phase switching frequency, the output ripple content is dominated by a 2 MHz component, which a given output capacitor bank filters far more effectively than the underlying 500 kHz per-phase ripple would allow. A four-phase controller with per-phase DCR current sensing keeps each of the four inductors converging on a roughly equal 20A share as the load steps between idle and full transient current.

Design Considerations

• Verify current-sharing accuracy against the controller datasheet, not just phase count. A controller that supports N phases doesn't guarantee tight current sharing on its own. Check the specified current-matching accuracy between phases, and confirm the recommended sense network (DCR RC values, or sense resistor value) is calculated correctly for your specific inductor and switching frequency.
• PCB layout gets more demanding, not less, as phase count grows. Each phase still has its own switching loop that needs the same tight-loop, small-switch-node-area treatment as a single-phase buck (see buck converter PCB layout), and now those loops need to be laid out symmetrically enough that trace resistance and parasitic inductance don't themselves become a source of current-sharing error between phases. A four- or six-phase VRM layout with phases mirrored or rotated around a central load point is common specifically to keep each phase's parasitic path length similar.
• Confirm the controller's phase-shedding behaviour, if present, matches your load profile. A design that spends most of its time at light load benefits significantly from phase shedding; a rail that's almost always near full load gets little benefit and adds unnecessary complexity by relying on it.
• Gate driver timing and dead-time control matter per phase, not just per converter. Each phase's high-side/low-side switch pair needs correctly sized dead time to avoid shoot-through, the same requirement as a single-phase synchronous buck (see MOSFET gate driver ICs and bootstrap design), multiplied across every phase in the design.
• Validate transient response and current sharing on the bench, not just in simulation. Component tolerances, layout asymmetry, and thermal gradients across the board all affect real current sharing in ways that are difficult to fully capture before hardware exists.

For point-of-load rails where phase count, current-sharing accuracy, and layout all need to come together on a production board, Zeus Design's electronics design team handles multiphase power design from topology and controller selection through to a manufacturable, EMC-compliant layout.

Common Mistakes

• Choosing phase count from a reference design without verifying against the actual load profile. A phase count sized for someone else's peak current and transient requirements may be needlessly complex (and costly) for a lighter rail, or inadequate for a heavier one. Size phase count to your own current and transient targets.
• Assuming ripple cancellation eliminates the need for output capacitance analysis. Interleaving reduces required output capacitance for a given ripple target; it does not remove the need to calculate it. The achievable cancellation depends on duty cycle and phase count, and falls short of the idealized case whenever the operating duty cycle sits away from the ideal cancellation points.
• Treating DCR sensing as inherently accurate without checking temperature compensation. Inductor DCR varies with temperature (copper's resistance rises with heat), and an RC sense network without temperature compensation can report current inaccurately as the inductor heats up under load, degrading current-sharing accuracy exactly when it matters most.
• Laying out phases asymmetrically and expecting the current-sharing loop to fully compensate. A current-sharing loop corrects for measured imbalance, but large layout-driven differences in trace resistance or thermal gradient between phases push the loop harder and can still leave one phase running hotter in practice, even with active balancing engaged.
• Ignoring light-load efficiency when every phase runs continuously. Without phase shedding, a multiphase converter running well below its rated current keeps every phase switching at a very low, inefficient duty cycle, which can make light-load efficiency noticeably worse than a single-phase design sized closer to the actual light-load current.