How Do You Design a Hierarchical Schematic in KiCad?

Detailed Explanation

A flat, single-sheet schematic works well for simple designs, but once a project grows past a certain size — or is naturally modular, with clearly separable functional blocks like a power supply, an MCU core, and an analog front-end — a hierarchical schematic keeps the design navigable and reviewable. For the general schematic capture and layout workflow this extends, see how to use KiCad: schematic entry and PCB layout workflow.

Sheet Symbols and Sub-Sheets

A hierarchical design starts with a sheet symbol, placed on the top-level schematic via Place → Sheet. Drawing a sheet symbol creates (or links to, if reused) a separate .kicad_sch file representing that sub-circuit's own schematic — a self-contained page with its own components, wiring, and local labels, opened by double-clicking the sheet symbol from the parent sheet. A design can nest sheets multiple levels deep, though most practical designs stay at one or two levels: a top-level "block diagram" sheet containing sheet symbols for each major sub-circuit, with each sub-circuit's own detail on its own sheet.

Hierarchical Labels and Sheet Pins

Connecting signals between the top-level sheet and a sub-sheet uses hierarchical labels — placed inside the sub-sheet on any net that needs to be visible to the parent. Each hierarchical label automatically creates a matching sheet pin on that sheet's symbol on the parent schematic, which the parent-level wiring then connects to like any other schematic pin. This is the mechanism that keeps hierarchical connections explicit and scoped: a hierarchical label only connects within its own sheet's hierarchy (visible to its parent sheet and to sibling instances of the same sub-sheet), not to an identically-named label on a completely unrelated sheet elsewhere in the design.

Hierarchical Labels vs Global Labels

KiCad's global labels are a different tool with a different scope: a global label connects to any other global label anywhere in the entire project that shares the same text, regardless of sheet hierarchy — no sheet pins or hierarchical structure involved. This makes global labels convenient for signals that genuinely need to reach anywhere in the design (many designs use them, or dedicated power symbols, for rails like +3V3 or GND), but that same reach is a liability if used carelessly: two unrelated sub-circuits that happen to reuse the same global label text will be silently connected, and KiCad's Electrical Rules Check will not flag this as an error because, as far as ERC is concerned, that connection was intentional. The general rule: prefer hierarchical labels and sheet pins for anything genuinely local to a functional block, and reserve global labels for signals that are deliberately meant to be project-wide.

Reusing Sub-Sheets

A single sub-sheet .kicad_sch file can be instantiated more than once on the parent sheet — useful for a design with repeated identical blocks, such as several identical sensor channels or LED driver stages. Each sheet symbol instance gets its own annotation (reference designators are assigned per-instance), but the underlying schematic content is shared: editing a component or wire on one instance's sub-sheet changes it for every instance simultaneously. This is a significant time-saver for genuinely repeated blocks, but it also means a hierarchical design with reused sheets is not the right tool for sub-circuits that are similar but need small per-instance differences — those are better handled as separate, non-shared sheets even if it means some duplicated schematic content.

Flattening for PCB Layout

Regardless of how many sheets a schematic is split across, KiCad flattens the complete hierarchy into a single netlist before PCB layout begins — the PCB editor has no concept of schematic sheets, only one unified list of components and their connections. Sheet structure is purely an organisational and readability tool at the schematic-capture stage; it has no effect on the resulting board's layers, footprint placement, routing, or the Gerber and drill files exported for fabrication.

Design Considerations

• Split sheets along functional boundaries, not by an arbitrary component count. A power supply, an MCU/peripheral core, and an analog front-end are natural sheet boundaries because each one is reviewable and testable somewhat independently — splitting a schematic purely to keep each sheet under some component-count target tends to produce awkward, hard-to-follow boundaries instead.
• Default to hierarchical labels; use global labels sparingly and deliberately. The scoping that hierarchical labels provide is a genuine safety net against accidental cross-connections between unrelated sub-circuits — a benefit worth keeping unless a signal truly needs project-wide reach.
• Use repeated sheet instances only for genuinely identical sub-circuits. If two blocks are similar but need even small differences, model them as separate sheets rather than fighting the shared-content behaviour of a reused sheet instance. Zeus Design structures complex multi-block schematics and PCB layouts, including hierarchical KiCad designs, for production electronics.
• Name hierarchical labels consistently and descriptively. Because the label text is what KiCad matches when generating sheet pins and connections, a consistent, unambiguous naming convention (e.g. matching the label text to the net's function rather than an abbreviation only the original designer would recognise) pays off directly when the schematic is reviewed or handed to another engineer.

Common Mistakes

• Reaching for global labels as a default instead of hierarchical labels, losing the scoping protection hierarchical design is meant to provide and risking silent, unintended net connections between unrelated sheets that happen to reuse the same label text.
• Splitting sheets by component count rather than functional boundary, producing a hierarchy that doesn't actually make the design easier to understand or review.
• Forgetting that a reused sheet instance shares its underlying schematic content. Editing what looks like "one" instance of a repeated sub-circuit changes every instance — a surprise for anyone expecting per-instance customisation without understanding this behaviour first.
• Assuming hierarchy affects PCB layout or fabrication output. It doesn't — the netlist is fully flattened before layout, so there's no risk in choosing a sheet structure based purely on schematic readability rather than any downstream layout concern.

For the general KiCad workflow this fits into, see how to use KiCad: schematic entry and PCB layout workflow. For managing the symbols and footprints used across a hierarchical design's sheets, see how do you create and manage KiCad footprint and symbol libraries?