How to Use KiCad: Schematic Entry and PCB Layout Workflow

Detailed Explanation

KiCad is a free, open-source EDA (electronic design automation) suite capable of professional-quality PCB design. It covers the complete workflow from schematic entry to fabrication output and runs on Windows, macOS, and Linux. For a conceptual overview of the PCB design process, see What Is PCB Design?.

The design flow in KiCad moves through five sequential stages:

1. Schematic entry — drawing the circuit's logic in the Schematic Editor
2. Footprint assignment — linking each symbol to its physical land pattern
3. PCB transfer — importing the netlist via Update PCB from Schematic
4. Board layout — placing components and routing copper traces
5. Fabrication output — generating Gerbers, drill files, and assembly data

Project Structure

A KiCad project is a folder containing three core files:

All three are plain text, which makes version control with Git straightforward. Create a new project via File → New Project in the KiCad project manager. This creates the project folder and skeleton files, and opens the manager showing buttons for each editor.

Schematic Entry

Open the Schematic Editor from the project manager. The core tasks are placing component symbols, connecting them with wires, and assigning net names.

Adding symbols: Press A to open the symbol chooser. KiCad ships an extensive built-in library covering standard passives, logic ICs, common MCU families, and connectors. Search by part number or keyword. After placing a symbol, press E to open its properties and set values (resistance, capacitance, reference designator, etc.).

Wiring: Press W to start a wire from any pin; click to change direction and double-click (or press Escape) to end it. Wires connect when they share an endpoint or cross with a junction dot. For nets that span large distances or multiple sheets, press L to add a net label instead of running a long wire — any two pins with the same label name are electrically connected.

Power symbols: Press P to add a power symbol (VCC, GND, +3V3, etc.) rather than wiring distant components to a single long power rail. Power symbols define global nets by name across the entire project.

ERC: Before moving to layout, run Inspect → Electrical Rules Checker. ERC catches unconnected pins, conflicting output drivers on the same net, and missing power connections. Resolve every ERC error before transferring to the PCB Editor — a schematic error that reaches the layout stage is significantly harder to diagnose. For an explanation of the most common KiCad ERC messages, see the forum discussion on PWR_PIN and pin-not-connected errors.

Footprint Assignment

Each symbol must link to a footprint — the copper pad layout for that package — before the PCB can be populated. In KiCad 8, assign footprints per-symbol: select a component, press E to open its properties, and click the Footprint field to launch the footprint browser. Search by IPC package designation or keyword (e.g. SOT-23, 0402, QFP-48).

KiCad's official footprint library (KiCad_Footprints) follows IPC-7351 land pattern conventions and covers the vast majority of standard through-hole and SMD packages. For non-standard or proprietary packages, create a custom footprint using the Footprint Editor (Tools → Footprint Editor). See How Do You Create and Manage KiCad Footprint and Symbol Libraries? for a complete guide to creating custom symbols and footprints, organising project vs global libraries, and version-controlling library files.

For a full explanation of why symbols and footprints are separate entities, see PCB Footprint vs Schematic Symbol: What Is the Difference?.

Transferring to the PCB Editor

Open the PCB Editor (.kicad_pcb) and select Tools → Update PCB from Schematic (default shortcut F8). KiCad reads the current schematic netlist and drops all new components as unplaced footprints in the corner of the board canvas, while preserving the placement and routing of any parts that haven't changed since the last update.

Unplaced components appear with ratsnest lines — thin diagonal lines indicating which pads must ultimately be connected by copper. Before placing components, draw the board outline: switch to the Edge.Cuts layer and draw a rectangle or polygon that defines the physical board boundary.

Board Setup

Before placing components, configure design rules in Edit → Board Setup (Ctrl+Shift+B). The key settings:

• Design Rules → Constraints: minimum clearance, minimum track width, and minimum via drill diameter. A common starting point for standard PCB fabs is 0.15 mm minimum track/space and 0.3 mm minimum drill diameter, though capabilities vary by process tier — check your fab's published rules.
• Board Stackup: define layer count (typically 2 for simple designs, 4 or more for high-speed or dense boards), copper weight (35 µm / 1 oz is standard for signal layers), and dielectric material if controlled impedance is required.

Many fabrication houses publish .kicad_dru design rule files that import directly into Board Setup, eliminating manual entry. Check your fab's website for their KiCad design rule file before setting constraints by hand.

Component Placement

Good placement precedes routing. The principles — signal flow, thermal management, and assembly constraints — are covered in PCB Component Placement: Best Practices and Common Pitfalls. In KiCad:

• G — grab component (moves while maintaining ratsnest visual connections)
• M — move freely without ratsnest constraint
• R — rotate 90°; enter an exact angle via properties (E)
• F — flip to the other board side

Watch the ratsnest density as you move parts: placement that minimises ratsnest crossings almost always produces shorter, cleaner routing. Pressing X from a ratsnest line immediately starts routing that connection — useful for checking whether a placement is workable before committing to it.

Interactive Routing

Press X to start routing a single trace from any pad. KiCad's interactive router respects existing copper and snaps to 45° corners by default (change to 90°, 45°, or free-angle in Route → Interactive Router Settings).

For denser boards, switch to Push and Shove mode via the Route menu: the router actively displaces existing traces to make room for the new one, avoiding the need to manually reroute when a placement change creates conflicts.

Useful shortcuts during routing:

• W — cycle between preset track widths (configured in Board Setup → Design Rules → Pre-defined Sizes)
• V — place a via and switch routing layer
• U — select the connected track segment to inspect or modify routed connections

Define track widths for power traces in Board Setup → Pre-defined Sizes before routing begins, so width selection is a single keystroke rather than a manual entry. See How Do You Calculate PCB Trace Width for Current Capacity? for IPC-2152-based sizing guidance.

Design Rule Check

Run Inspect → Design Rules Checker after routing to verify the complete layout against Board Setup constraints. KiCad 8 also flags violations in real time during routing — error markers appear on the canvas as you place copper — but the full DRC run catches courtyard overlaps, silkscreen conflicts, and unconnected nets that the real-time check doesn't surface incrementally.

Address every DRC error before generating outputs — fabrication houses may reject a board with rule violations, and some errors (minimum annular ring violations, clearance shorts) cause manufacturing failures. For a breakdown of the most common DRC error types, see What Are PCB Design Rules (DRC)?. For a worked example of annular ring and acid-trap DRC failures in KiCad, see the forum thread on pcb-drc-keeps-failing-annular-ring-acid-trap.

Generating Fabrication Outputs

Once DRC passes cleanly, generate the fabrication package from File → Fabrication Outputs:

1. Gerbers: File → Fabrication Outputs → Gerbers. Select all copper layers, solder mask (front and back), silkscreen (front and back), and Edge.Cuts. Click Plot to write .gbr files.
2. Drill file: File → Fabrication Outputs → Drill Files. Generate both a plated-through-hole (PTH) and a non-plated (NPTH) drill file in Excellon format.
3. Assembly files: File → Fabrication Outputs → Component Placement (pick-and-place file) and File → Fabrication Outputs → BOM.

Always verify the Gerber output using File → Open Gerber Viewer or your fab's online preview before submitting. Gerber configuration errors — missing layers, incorrect origin, wrong layer-to-file mapping — are invisible in the PCB layout view but immediately apparent in a Gerber viewer. For a complete breakdown of what each fabrication file contains and when each is needed, see What Files Do You Need to Send a PCB for Fabrication?. For detailed KiCad plot settings, drill file configuration, coordinate origin alignment, and step-by-step GerbView verification, see How to Export Gerber Files from KiCad for PCB Fabrication.

Design Considerations

• Assign footprints before transferring to the PCB Editor. Symbols with missing footprints appear as unplaceable pads in the layout. Completing footprint assignment during or immediately after schematic capture avoids a second round-trip back to the schematic editor.
• Import your fab's design rule file. The KiCad default minimum clearance and via sizes are conservative but may not match your chosen fab's process tier. Importing their .kicad_dru file ensures every DRC pass reflects actual manufacturing constraints.
• Use net classes for power and RF traces. Define net classes in Board Setup → Design Rules → Net Classes and assign high-current or RF nets to a class with appropriate minimum track widths. The router then automatically applies the correct width when you begin routing a net in that class.
• Define the board outline before placement. Without a closed Edge.Cuts boundary, DRC cannot check courtyard clearances against the board edge, and the 3D Viewer cannot render the correct board shape. Draw the outline first, then place components within it.
• Use the 3D Viewer as a placement sanity check. Open View → 3D Viewer periodically to check for mechanical fit — tall components shadowing short ones, connector overhang at the board edge, and mounting hole conflicts are far easier to spot in 3D than in the 2D canvas view. Most official KiCad footprints include 3D models; verify that custom footprints have 3D model paths assigned if the 3D check is important.
• Version-control the project folder. KiCad's plain-text .kicad_sch and .kicad_pcb files produce readable diffs. Commit after each milestone — schematic ERC clear, footprints assigned, placement complete, routing complete, DRC clean — so each stage can be restored independently. For complex or high-speed designs that require controlled impedance, dense BGA routing, or DFM review, Zeus Design's PCB design service covers the complete schematic-to-fabrication workflow.

Common Mistakes

• Skipping ERC before moving to layout. Schematic errors that are trivial to fix in the Schematic Editor — an unconnected power pin, a missing net label on one side of a bus — become confusing floating ratsnest lines or phantom unconnected nets in the PCB Editor, where the schematic context that explains them is not visible.
• Changing footprints after routing has started. Any footprint replacement triggers an Update PCB from Schematic that drops the new footprint as an unplaced component, forcing re-placement and re-routing of all connections to that part. Finalise footprint assignments before starting layout.
• Not checking the fab's design rules before routing. Default KiCad constraints do not match every fabrication house's process. Routing a board to 0.1 mm track/space and then discovering the fab requires 0.13 mm minimum means rerouting dense areas.
• Submitting Gerbers without the drill file. KiCad generates the drill file separately from the Gerber plot — it is not included in the Plot output. Submitting Gerbers alone means the fabrication house has no drill data; vias and through-hole pads will be absent from the manufactured board.
• Not verifying Gerber output before submission. A misconfigured Gerber export — wrong coordinate origin, missing a copper layer, incorrect solder mask polarity — is not visible in the KiCad PCB Editor but is immediately obvious in a Gerber viewer. Verify every export before sending to the fab.
• Ignoring courtyard overlaps. KiCad DRC flags courtyard overlaps between adjacent components. Ignoring these errors is tempting when the overlap appears minor in the 2D view, but courtyard overlaps can cause pick-and-place head collisions during assembly and component shift on the board. Resolve overlaps by adjusting placement or, for intentionally tight fits, by modifying the footprint courtyard boundary.