How Do You Route Controlled-Impedance and Differential Pairs in KiCad?

Detailed Explanation

Controlled-impedance and differential pair routing come up on nearly every board carrying USB, Ethernet, high-speed digital buses, or RF signal paths — and KiCad's tooling for it is capable but requires understanding three separate features working together, rather than a single "make this impedance-controlled" checkbox. For the underlying electrical concept, see What Is Controlled Impedance PCB Design? and Signal Integrity in PCB Design; this page covers the practical KiCad 8 workflow for implementing it.

Step 1: Define Net Classes

Net Classes (Board Setup → Design Rules → Net Classes) group nets that share the same electrical requirements — track width, clearance, and via size. Create a dedicated net class for each impedance-controlled signal group (e.g. "USB_DP", "Ethernet_Diff", "RF_50ohm") rather than relying on the default class, and assign the calculated track width from Step 2 to that class. This ensures the interactive router enforces the correct geometry automatically as you route, rather than requiring manual width verification on every segment.

Step 2: Calculate Target Trace Geometry with the PCB Calculator

KiCad's PCB Calculator utility (a standalone tool bundled with KiCad, also reachable via Tools → External Plugins in some configurations) includes dedicated calculators for microstrip, stripline, and differential pair impedance. Enter:

• Dielectric constant (Er) and loss tangent for your actual laminate — request these from your fabricator for the specific material and frequency range, rather than using the tool's generic FR4 default
• Copper weight (commonly 0.5 oz / 17 µm or 1 oz / 35 µm) for the relevant layer
• Substrate height to the nearest reference plane, from your confirmed stackup
• Target impedance — commonly 50 Ω single-ended or 90–100 Ω differential for USB/Ethernet-class signals (confirm the specific target for your signal standard; USB 2.0 D+/D– targets 90 Ω differential, USB 3.x SuperSpeed pairs target 85 Ω)

The calculator outputs the trace width (and, for differential pairs, the width and gap together) needed to hit that target impedance given your actual stackup. Generic FR4 defaults can produce a result 10–15% off from what a specific fabricator's actual material properties deliver — this is the most common reason a "controlled impedance" board measures outside its intended tolerance after fabrication. Confirm final values directly with your fabricator's stackup documentation before finalising design rules.

Step 3: Route Differential Pairs with the Interactive Router

Once Net Classes carry the correct width/gap values, KiCad's differential pair router (shortcut 6, or Route → Differential Pair) routes both conductors of a pair together, maintaining consistent gap and automatically routing around obstacles as a matched unit rather than requiring each trace to be routed and matched separately. Key behaviours:

• The router maintains the gap value from the assigned net class as you route
• Both traces of the pair move together when adjusting placement, keeping them physically adjacent (a requirement for differential signalling — pairs routed far apart lose their common-mode noise rejection benefit)
• Via transitions on a differential pair should use closely spaced vias for both conductors to minimise the impedance discontinuity at the layer change

Step 4: Length Tuning

Differential pairs (and length-matched single-ended buses, such as parallel memory interfaces) often require intra-pair or inter-pair length matching within a tolerance the target protocol specifies. KiCad's router includes a length-tuning mode (accessible from the same differential pair router, or via the single-track length-tuning tool for non-differential nets) that inserts accordion (sawtooth) or trombone meanders to add controlled extra length to the shorter trace until both match within the configured tolerance.

Set the target length tolerance in the net class or via the length-tuning dialog before tuning — KiCad displays the current length delta live as you adjust the meander, letting you tune to the target without repeatedly measuring manually. For USB 2.0 High Speed, intra-pair skew should typically stay below roughly 150 ps (approximately 15 mm on FR4, though the exact figure depends on your stackup's propagation velocity); for higher-speed interfaces the tolerance tightens correspondingly — confirm the specific tolerance for your protocol against its specification rather than assuming a universal figure applies.

Via Stitching for Reference Plane Continuity

Controlled-impedance traces depend on an unbroken reference plane directly beneath them. Where a differential pair or high-speed single-ended trace must cross a plane split or change reference planes at a layer transition, place stitching vias near the signal via to give return current a low-impedance path across the discontinuity — an isolated signal via with no nearby ground stitching forces return current to detour, increasing loop area and degrading the very impedance control the routing effort was meant to achieve.

Design Considerations

• Confirm your fabricator's actual stackup parameters before calculating target trace widths — this single step prevents the most common real-world impedance miss. Zeus Design validates PCB stackup and impedance targets against the actual fabricator's process data as standard practice on controlled-impedance designs.
• Set Net Classes before routing, not after. Retrofitting correct trace width and gap onto an already-routed differential pair is far more disruptive than starting with the class correctly configured.
• Route differential pairs as a matched unit from the start, rather than routing each conductor independently and attempting to reconcile length and spacing afterward.
• Budget board space for length-tuning meanders during placement, particularly near connectors where multiple differential pairs converge (USB-C, Ethernet) — a tight placement that leaves no room for accordion tuning forces compromises late in layout.
• Verify via stitching density near any reference-plane transition that a controlled-impedance trace must cross — this is easy to overlook once the primary routing is complete.

Common Mistakes

• Using KiCad's default FR4 dielectric constant without confirming it against the actual fabricator's material. This is the single largest source of a board's measured impedance missing its design target after fabrication.
• Routing a differential pair as two independently-routed single-ended traces rather than using the dedicated differential pair router — this makes it far harder to maintain a consistent gap and matched length throughout the route, especially around obstacles.
• Setting trace width and gap directly in the routing tool without first calculating them from the actual stackup — a "reasonable-looking" width/gap combination chosen by eye rarely lands on the intended impedance target.
• Ignoring via stitching where a controlled-impedance trace crosses a plane split or layer transition, leaving the return path discontinuous exactly where impedance control matters most.
• Length-tuning to an arbitrary "close enough" visual match rather than the specific tolerance the target protocol's specification actually requires — different interfaces (USB 2.0 HS, USB 3.x, Ethernet, DDR memory) have meaningfully different skew tolerances, and over- or under-tuning both carry real costs (respins for the former, marginal signal integrity for the latter).